"Not many semiconductor makers will qualify to go to 90nm"

EDN Asia: How do you compare Altera's 90nm products such as Stratix 2 and Cyclone 2 with Xilinx 90nm products such as Spartan 3 or Virtex 4?

Lee: One of the greatest challenges in making products at 90nm is using low-k. Xilinx and its foundry partner UMC use FSG instead of low-k. However, Altera and our foundry partner TSMC have mastered the low-k technology. Our 90nm products use low-k, against Xilinx products, which do not. Besides, we have used 12" wafers, while Xilinx has used 8" wafers.

EDN Asia: The SIA roadmap doesn't seem to suggest that low-k or 12Ó is an absolute necessity at 90nm.

Lee: Having low performance at higher technological node does not make sense. If you use FSG, the performance is at least 10 percent below that using low-k. If you use 8Ó, you are not giving the best price/performance to your customer. We used FSG at 130 micron. We waited for low-k technology to mature before entering into it. Xilinx introduced its 90nm product too early. Our yield at 90nm is 90 percent. Six months before we shipped the first Stratix 2, we had attained a yield of 85 percent. Xilinx and UMC are still struggling with 8Ó and FSG at 90nm, while TSMC qualified for 12Ó and 90nm as long back as July 2003.

EDN Asia: Xilinx introduced its 90nm products one-and-a-half years before Altera. It has already sold 500,000 units of Spartan 3. What kind of lead has this given Xilinx over Altera?

Lee: Technologically we are far ahead of Xilinx and Xilinx will find it difficult to overtake us. We have leadership position in low-k, 90nm. Xilinx will have to go to low-k to catch up with us.





EDN Asia: The market share of Xilinx is about 20 percent more than that of Altera. Does Altera envisage overtaking Xilinx in market share?

Lee: The current market is almost entirely composed of products at earlier nodes, such as 180nm and 130nm. When 90nm products become mainstream, Altera shall overtake Xilinx in market share. We expect 90nm products becoming mainstream around Q405.

EDN Asia: What were the greatest challenges you faced in moving to 90nm?

Lee: There are three new and main challenges. These are: first, design and tool costs are very high; second, transistor leakage is very high causing power management problems; and third, the volume to justify 90nm is very high. Not many semiconductor makers will qualify to go to 90nm.

EDN Asia: Are you looking at any new application areas with your latest products?

Lee: In 2003, the CMOS digital logic market was worth $26 billion, of which merely 10 percent was constituted by programmable logic. The FPGA low penetration is primarily because not all designers are aware that many of the designs they do with ASICs can be done easier, faster and cheaper with FPGAs. Altera is trying to educate designers in how FPGAs can increase their efficiency while cutting down costs. Our Cyclone range of products will essentially drive programmable logic use into high volume areas where traditionally ASICs have reigned supreme. There is a fundamental change in the chip market structure. Earlier the market was PC driven, in future it will be digital-consumer driven. It may not be an exaggeration to say that with our present product range and those on the anvil programmable logic can address most of the $26 billion digital logic market.

You can reach Kirtimaya Varma at kirti.varma@rbi-asia.com