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EDA at crossroads

( 01 Aug 2004 )
By Kirtimaya Varma, Editor-in-Chief

As EDA moves ahead, will it follow its path of the last 20 years or radically change its course? The answer is as unclear as whether Moore's Law has hit a wall. Some companies, Cadence for instance, say that EDA will evolve as continuation of the past. This viewpoint is based on the belief that the future is the same as the past when every two years things changed because of Moore's Law, but there was no need to change EDA from its evolutionary course. Some companies, CoWare for instance, believe that EDA has reached an inflection point, and revolutionary new methodologies and technologies are needed to meet new design challenges. Yet other companies, Tensilica for instance, take a middle course. They see EDA advancing through some fundamental shifts in design infrastructure. These shifts are not revolutionary, but built on top of the traditional industry.
I think there are two issues EDA will have to address as it moves forward. The first is that designers will use pre-defined IP blocks more often and in larger quantities to increase design efficiency, accelerate time of design, and reduce time to market. A large portion of chip design will be based on standard IP, with some specialty elements in every design. Second, deeper into nanometrics, the amount of software contents on chips will explode, which current generation design tools are not cognizant of.

I would view the situation as follows. The current EDA tools are sufficient to address 0.18 and 0.13 micron, which are mainstream design nodes today, and will continue to be mainstream next 3 or 4 years at least, if not more, notwithstanding leading edge design excursions into 90 and 65nm technologies. This viewpoint stems from the fact that at 90nm and beyond ROI is so poor that companies will continue to look for profitability and raison d'etre at older nodes, even as they may want to be presentÑmerely presentÑat the latest node.

EDA tools will continue with their evolutionary changes, and satisfy most customers. However, when main-stream design moves to 90nm and beyond, connections between EDA and IP will radically alter not only EDA technology but also market. The value proposition of EDA is to accelerate design and improve efficiency. IP does the same things in a different way. To design efficiently, will the customer quickly assemble pre-defined IP blocks, or start from the scratch using HDL? If economics, and not technology, will drive industry into deep submicron, as is commonly believed, then the customer is likely to use pre-defined IP blocks, such as the ones available from ARM, MIPS and Tensilica. As an enabling technology, IP has an edge over EDA, because the amount of work needed in having an IP validated, and ensuring its functionality, testability, manufac-turability and configurability is significantly less than creating functional blocks for EDA tools. Will there be any differentiating technology? I think when economics does drive the industry, differentiating technologies will be less in demand than enabling ones.

EDA has defied the cyclical nature of the electronics industry. Except in 2002, EDA has consistently posted growth. However, several techno-logical factors have concurred to make EDA future uncertain. Designing with pre-defined IP blocks is just one of them. Growth in FPGA capabilities, leading to a great fall in ASIC design starts, is another. Yet another factor is that what used to be separate chips is now part of the same chip. For instance, memory and microcontroller are increasingly being embedded on a chip rather than being designed separately.

The most pessimistic estimate coming from some analysts is that EDA growth is doubtful. Not all are so pessimistic. In 2003, EDA grew by just 3 percent, as against semiconductor growth of over 15 percent. In 2004, EDA growth has been flat till mid-year, even as semiconductor is projected to grow by a whopping 27 percent. Not all are so pessimistic. However, all agree that EDA is at crossroads from where charting its future path is uncertain.

You can reach Kirtimaya Varma at kirti.varma@rbi-asia.com

 
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