CAD for chip and package co-design

In the modern electronics world, there is an ever-increasing demand for high speed, compact and low cost systems. Shrinking feature sizes in silicon process technologies can address the above requirements only to a certain extent, and in reality, bottlenecks for area and performance are now moving from chip domain to package domain. This necessitates the concurrent design of chip and package which is sometimes called Chip and Package Co-design. Die size reduction and performance improvement of an integrated circuit (IC) is possible by choosing an optimal package and by optimizing the die interfaces in package environment.

Meanwhile, due to progress in packaging technologies, designers can now integrate a system with more than one die in a single package which is called system-in-package (SiP). Integration can be done by various means; stacking multiple dies, side-by-side placement and any combinations of these. The die-attach mechanism can be either flip-chip or wire bond. SiP offers a provision to layout passive components such as inductors and capacitors on package to achieve high Q-factors at radio frequencies (RF). SiP can integrate multi-technology dies in one package, and offers higher levels of integration compared to conventional system-on-chip (SOC).



To design compact, low cost and high performance SiP, Chip and Package Co-design is imperative. Chip and Package Co-design comprises design tasks both from chip domain and package domain. This interdisciplinary nature brings in additional complexity to computer aided design (CAD) tools and flows used for this purpose. This article describes some challenges in CAD for Chip and Package Co-design.



Co-design tasks are of 2 types: (i) Die Co-design: Optimized design of individual dies in package environment and (ii) SiP Design: integration of different dies to build a complete system. In both the cases the target is to optimize package layout and chip interfaces – both from physical and electrical standpoint.

Die Co-design

From the physical standpoint, Co-design includes the optimal placement of IO pad cells or macros on the die for any assembly technology (wire bond or flip chip). It also needs to ensure an optimum placement of bumps to achieve a feasible Redistribution layer (RDL) routing. The target is to (i) reduce die size (ii) meet assembly design rules and (iii) minimize the number of package substrate routing layers. Electrically, the performance of die interfaces in package environment needs to be verified. This requires co-simulation of critical die interfaces with the package parasitics. Co-simulation must also target elimination of signal integrity (SI) issues such as mutual coupling between package interconnects.

SiP Design

SiP design tasks are typically driven by the system architect. These involve trade-off analysis between single-die and multi-die combinations and different ways to place and connect dies. Design considerations for trade-off include (i) optimum placement of dies to meet timing margin and thermal budget (ii) optimized substrate routing (iii) ensuring signal integrity during signal transmission over the interconnects. As frequency increases SI issues such as reflection, crosstalk and electro magnetic interference (EMI) become dominant and degrade the performance of the system considerably. So the SiP substrate routing must be done carefully to prevent the SI issues.

CAD challenges – Integration

Being an interdisciplinary domain, Co-design CAD flow should allow integration of chip and package design flows in one environment. First step in Co-design is to specify the connectivity between die(s) and package. Flow interfaces for connectivity entry should support both language based approach (as in digital design) and schematic entry based approach (as in analog design). Connectivity entry must have links to physical implementation and electrical verification tools.

Also, the flow must provide a means to exchange physical and electrical information from one domain to the other. For example for die layout optimization, designer must be able to exchange die interface layout data between die and package layout tools. Similarly, for electrical verification, there must be a provision to import package parasitics into chip simulation environment to perform co-simulation. Also, the flow must support a tight link between electrical verification and physical implementation tools in package domain. Thus a designer must be able to verify a system electrically, and specify the constraints for physical implementation.

CAD challenges – Early exploration

Co-design flow must include tools to check the feasibility of a system from bare specification. The feasibility of a system should be checked in electrical, thermal and physical aspects. This helps minimizing design iterations. For electrical feasibility analysis, estimated package parasitics must be available early in the design cycle. So it is required to maintain repositories of estimated models for standard packages. Also, the flow should integrate parasitic extraction tool for accurate extraction over a wide range of frequencies.

CAD challenges – Mix of environments

For system level integration, CAD flow must support seamless integration of different dies coming from various chip design teams into packaging environment. CAD flow should offer seamless import and export of data from various environments and reliable integration. Sometimes, package and chip designs are done in different operating systems; for example, traditionally package design is done in Microsoft windows platform while chip design is in Unix or Linux platforms. CAD flow for Co-design should also support such scenarios.

Conclusion

In the coming years, SiPs will find extensive application in consumer electronics products. To design robust SiPs CAD tools and flows meeting the above challenges need to evolve. There are some efforts by leading EDA vendors to develop tools in this domain ushering the SiP era.