Advances in VLSI manufacturing have enabled designers to place tens of millions of gates on a single die at a reasonable cost and create Systems-on-Chip (SOCs). An SOC, which can make use of reusable cores, is a reasonably complete, functional subsystem. In general, an SOC contains a wide variety of elements: processor core, embedded memory, random logic, and analog circuitry, as well as peripherals. The emergence of SOC technology has ushered in a spectrum of opportunities to build low-power, miniaturized appliances. Simultaneously, SOC design offers challenges associated with deep sub-micron complexities, faster timing closure requirements, testability subtleties, and time-to-market issues. In STMicroelectronics India Design Center, researchers and engineers deal with these challenges and participate in SOC design for home entertainment, personal multimedia, communication infrastructure, computer peripherals, and automotive applications.
SOC Design Strategy
In order to deal with shortened product life cycles in a competitive market, STMicroelectronics has been emphasizing reducing design cycle time. The Company is developing new design methodologies for faster implementation, verification, and testing. ST’s engineers have defined and are continually refining systematic SOC design strategies for architecture, front-end and back-end implementation, DFT, validation, and overall integration.
Architecture Phase: Based on the specification of an intended design, ST’s engineers implement timing-critical components like CPUs or function-critical analog components as hard macros, in order to characterize and protect critical paths. On the other hand, the engineers can implement functions without any critical-timing requirements as soft or firm macros. Along with a processor core, the system bus is also defined in the architecture phase. ST’s engineers in its India Design Center architected the STV0684, a coprocessor for UXGA-resolution CMOS sensors. The coprocessor incorporates image-processing functions (e.g., color interpretation), captures still picture of up to 2 mega-pixels and supports streaming video up to VGA resolution. Integrating all of the blocks of an SOC becomes somewhat simpler when standard (e.g., AMBA AHB, APB) buses and plug-and-play blocks (e.g., DMA controller, decoder), as well as application-specific IPs (e.g., 802.11, USB, Bluetooth) are used.
Design Phase: ST invested significant R&D effort in its India center for the design of Palinuro, a complex single-chip GPS positioning system. The SOC is manufactured in ST’s RFCMOS8 process and combines RF, baseband, and micro-controller units. In such projects, once the architecture is finalized, engineers create an RTL design by modeling the device’s function primarily using VHDL code. A design compiler then synthesizes and optimizes the gate-level netlist, which shows design connectivity. Synthesis, using commercial Electronic Design Automation tools, is performed based on customer constraints---original RTL code may be modified in case of major violations; otherwise, timing optimization is done at the synthesis level. ST’s engineers use static-timing analysis exhaustively to validate the timing performance by checking all possible paths for timing violations without using logic simulation or test vectors. The designers verify setup, hold, recovery, removal, and other constraints and, if necessary, resynchonize the design using new timing constraints, if needed.
DFT Phase: In designing-for-testability (DFT), engineers use models of common physical defects (e.g., power or ground shorts, open interconnect on die) that may be introduced during fabrication or packaging,. An Automatic Test Pattern Generator (ATPG) creates test pattern sets automatically and determines the pattern’s effectiveness. Many ST projects in India have adopted internal scan design techniques, which simplifies pattern generation by dividing complex sequential designs into fully isolated combinational blocks, and then generates test vectors for high fault coverage. The engineers create test vectors to identify bridging faults, transition faults, and at-speed and IDDQ (high-current) problems in order to verify silicon performance avoid field rejection. For compilable memories, STMicroelectronics widely uses (Built-In Self Test) BIST solutions developed in India.
Physical Design Phase: Placement is the actual placing of macros and other standard cells on the chip established in floor-planning; whereas routing provides pin-to-pin connectivity. For projects like ST’s Atlas (SOC for DSL-based central office) and Quicksilver (SOC for Wireless-LAN), teams in India carried out physical design implementation and analysis. Timing-driven placement tries to place critical paths close together to reduce the net resistive/capacity (RC) delays and to meet timing constraints. Thereafter, an engineer performs clock-tree synthesis (CTS) to distribute clock signals to the clock pins using balanced trees. Taking advantage of clock skews helps improve design performance, reduce power consumption, increase reliability margin, and reduce simultaneous-switching problems. Engineers assignment-tracks to specify to the software which, within each global route cell, are to be used for an interconnect and to reduce the number of vias, whereas the detail router routes a small area at a time. Subsequently, engineers attempt to fix antenna violations, avoid crosstalk, perform design rule checks (DRC), ensure layout-versus-schematic (LVS) accuracy, and analyze power distribution. ST has adopted various parasitic extraction techniques for advanced process technologies including copper interconnect and low-K dielectric and after these are incorporated into the design, a correct-by-construction netlist is generated.
Validation Phase: Given the tens of millions of transistors on a chip, capturing the complexity of an SOC into an executable verification environment and then performing formal verification at every step of the design flow can become a mammoth task. Modeling performance around transactions and bus functional models facilitates in creating reusable verification code. ST’s STW21000, on which these techniques were used, is a cost-effective SOC that targets applications in 2.5G/3G wireless infrastructure equipment. A high-level of code coverage ensures the conformity of the design to specifications. Indian engineers have participated in validation/verification activity of this chip, which combines two quad-MACs, an ST140 DSP, and an ARM926 core that , together, provide a total of 7500 Million Instructions per Second (MIPS).
Platform Development Phase: While SOC devices are more complex than standard processors, a SOC-based design simplifies the end-system design because it integrates several previously distinct functions on a single chip. ST’s Nomadik family of application processors comprises SOCs making the vision of an open architecture for mobile multimedia a reality and driving the design of ultra-light, pocket-sized, multimedia-enabled mobile phones. The core processor in Nomadik is an ARM processor and around this, ST’s architecture defines intelligent accelerators whose role is to perform multimedia processing functions, including controlling sound and video. Beyond its chip-validation activity, STMicroelectronics India has been heavily involved in defining the software interface and design. Teams in India have been porting real-time operating systems, such as Symbian and Linux, onto Nomadik; developing software in high-level language integrating Java acceleration; and finally building Nomadik into a platform for a broad range of portable applications.
Technology Shrink
An SOC team in India recently shrunk the area of a decoder chip (ST5528cut1) by 30% without any change in netlist or functionality, but deploying state-of-the-art implementation and packaging techniques. The production cut of this 105 mm2 chip, with 38 million transistors and a wire-bonded BGA package, was in 0.13 micron. The detailed physical implementation involved the floor-planning of 187 hard macros and memories. Then, the chip contained 75 clock domains at the chip level which engineers in India needed to pursue careful clock-tree synthesis. In order to place around 200 digital 1.2V core power pads in the central portion of the chip, engineers used flip-chip packaging in a ‘central-bump-matrix’. This approach provided power directly to the metal5 and metal6 power-ground mesh. The overall implementation strategy was hierarchical, with block implementation done using a Monterey-Synopsys flow, an integrated approach that ST developed in India. For similar technology shrink activity, ST uses an array of implementation tools (e.g., Dolphin, Astro, Portal, Opus, Primetime, Calibre, Formality).
Conclusion
SOCs have found their way into a wide range of devices that include internet appliances, mobile phones, car information system, and set-top-boxes. High-speed simulation aids in SOC architectural analysis, as well as hardware-software co-verification. A key driver and enabler of SOC design is rapid construction of a chip using pre-verified IPs. By enforcing a consistent IP design process that ensures robustness in implementation, thoroughness in verification, and modularity/configurability in design, ST encourages IP reuse across various engineering groups in its India center and around the world. As ST had embraced sub-micron technologies, its teams are innovating to resolve power, voltage drop, electro-migration, and other issues. Over the last decade, STMicroelectronics India Center has matured from developing libraries and IPs to creating complete SOCs---SOCs for home entertainment, telecommunication, automotive, and a plethora of other applications.
Source: EDN Asia, a sister publication of EDN India
