The IEEE announced that it has approved SystemVerilog, IEEE Std 1800-2005, as a new standard and has approved Verilog, IEEE Std 1364-2005, as a revision to the popular Verilog hardware description language (HDL). SystemVerilog extends the Verilog language, the predominant language used for chip design, to address the growing complexity of electronic system and semiconductor designs. SystemVerilog is a unified language for hardware design, specification, and verification that was developed within the IEEE Standard Association's Corporate Program.
Johny Srouji, chair of the SystemVerilog 1800 Working Group and Verilog 1364 Working Group, said, ˇ°IEEE 1800 enhances the Verilog HDL to keep it at the cutting edge of the industry. It offers a more powerful, integrated, concise design and verification language, allowing engineers to deal with more complex design configurations, such as deeper pipelines, greater logic functionality and a higher abstract representation of the design using fewer lines of register transfer level code."
"The IEEE 1800 standard was developed in a very short period, twelve months, as a result of excellent collaboration and contributions of all working group members and underlying technical committees," said Chuck Adams, chair of the IEEE Standards Association (IEEE-SA) Corporate Advisory Group (CAG). "Accellera played a major and important role in enabling this achievement, through the donation of Accellera SystemVerilog 3.1a, in addition to continuous and outstanding cooperation with the IEEE 1800 group throughout the development of this standard."
IEEE
