Technologies, India In the modern electronics world, there is an ever-increasing demand for high speed, compact and low cost systems. Shrinking feature sizes in silicon process technologies can address the above requirements only to a certain extent, and in reality, bottlenecks for area and performance are now moving from chip domain to package domain. This necessitates the concurrent design of chip and package which is sometimes called Chip and Package Co-design. Die size reduction and performance improvement of an integrated circuit (IC) is possible by choosing an optimal package and by optimizing the die interfaces in package environment.
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