Embedded power in telecommunication and computing systems today faces the challenge of continuously increasing power density. While the power requirements go up, the space available for the power systems maintains constant at best. These requirements can only be met by better system efficiency.
Improvements can be realized on different levels—system, converter and device levels. New power architectures reduce losses on system level. Optimized converter topologies for ac-dc and dc/dc improve efficiency on converter level. New MOSFET technologies boost efficiency on device level. However, MOSFETs are key components of power converters. Better technologies allow more challenging operating conditions for an existing topology, i.e. increase in switching frequency, or even enable for a change to another topology.
Infineon’s OptiMOS 2 100V technology provides fast switching and low on-resistance as shown in
Figure 1. Additionally, the high speed series (HS-series) with ultralow gate charge offers a further 33 percent rise in speed for fast switching if needed.
Device concept of new OptiMOS 2 MOSFET seriesThe compensation principle for power MOSFETs was introduced in 1998 in commercially available products with the 600V CoolMOS Technology [1]. The basic principle behind the Rds(on). A reduction compared to conventional power MOSFETs is the compensation of additional n-drift region donors by acceptors located in p columns.
For breakdown voltages below 200V, trench field-plate MOSFETs are an excellent alternative. The application of a field plate improves the device’s performance. The device comprises a deep trench penetrating most of the ndrift region. An insulated deep source electrode, separated from the n-drift region by a thick oxide layer, acts as a field-plate and provides mobile charges required to balance the drift region donors under blocking conditions. The thick field-plate insulation has to withstand the full blocking voltage of the device at the trench bottom. Consequently, oxide thicknesses in the micron range have to be controlled carefully.
In contrast to standard MOS structures that exhibit a linearly decreasing electric field with a maximum at the body/drift region pn-junction, the field-plate principle leads to an almost constant field distribution, thereby reducing the necessary drift region length for a given breakdown voltage. In addition, the drift region doping can be increased, resulting in a clearly reduced on-state resistance. The Rds(on).A is even reduced below the so-called “silicon limit,” which is the on-resistance of an ideal abrupt p+n-junction at a given breakdown voltage. The combination of field plates together with the trench gate MOSFET-concept results in low ohmic and fast switching silicon technology.
Application benefitsIn embedded power systems three major applications for 100V power MOSFTEs are present: as synchronous rectifying switches of ac-dc front-ends with output voltages of 12 to 20V, as power switches in the 48V wide range rail, and as primary-side switches in isolated dc/dc converters operating from the 48V rail. While the Rds(on) is beneficial to all of the above applications, other features of the OptiMOS 2 100V technology apply more specifically to some of them.
The implementation of charge balancing enables the OptiMOS 2 100V technology to be strongly competitive. The technology allows for key parameters, such as Rds(on), Qg, Qgd, Crss/Ciss-ratio and high avalanche ruggedness simultaneously in a single device. The low Rds(on) (12.5mW(max) in D-Pak, 4.1mW(max) in D
2-Pak, 9mW(max) in SuperSO8) combined with fast-switching capabilities and high avalanche ruggedness makes the OptiMOS 2 100V a choice for safe, high performance, high power-density applications.
Avalanche ruggednessEven though inductive loads as they are present in motor control and similar applications are not present in embedded power systems, the capability of the MOSFET to safely handle avalanche events is essential. All of the above mentioned applications may face system failures caused by brownouts, lightning-strikes or other unforeseeable events, which finally drive the devices into avalanche. A solid avalanche ruggedness assures safe operation of the system even under those conditions.
On silicon technology level, two mechanisms can be found that provide the charge carriers during the avalanche event.
The first mechanism is related to the turn-on (latch-up) of the parasitic npn-transistor in the MOSFET. It is a non-thermal destruction, as it is caused by the current flow through the p-base. As soon as the voltage drop across this region is large enough to forward-bias the base-emitter barrier, the transistor turns on. This mechanism is self-amplifying and leads to a current limited avalanche characteristic. This limit is not favorable for a power MOSFET, as even very low energies are sufficient to destroy the device once the critical current is reached.
The second mechanism is related to avalanche generation of carriers. The over-voltage across the device is sufficient to accelerate single free electrons to a point where those can again generate free electrons resulting in a chain reaction. The energy dissipated in the device is spread out over the drift region. The limit for the avalanche capability of a device under this mechanism is given by the capability of the device to absorb (thermal) energy. This failure mechanism is known as thermal destruction.
Rugged devices fail due to thermal destruction and show characteristic curves as depicted in
Figure 2. Here, extrapolation lines are fitted to the average failure current points determined at various temperatures. The intersection point with the zero current line marks the intrinsic temperature of the device, which is a measure for the avalanche capability of a device. In
Figure 2 the avalanche capability of the new OPTIMOS 2 100V device in comparison with the previous technology is evident.
Immunity to dynamic turn-onThe biggest lever to reduce power-losses in a SMPS is to change the secondary-side rectification from a passive system using diodes to an active synchronous rectification (SR) using MOSFETs. For output voltages of 12 to 24V, depending on topology, 100V MOSFETs are the choice for SR. Due to its corresponding conduction losses, the Rds(on) is a key parameter for SR.
However the use of MOSFETs for the secondary side rectification comes with additional risks. The most prominent is the dynamic turn-on. In hard-switching topologies, very large dV/dt-values from drain to source may occur, when the device starts to block. This dV/dt couples to the gate via the capacitive Cgd/Cgs voltage divider and might dynamically turnon the device (cp. Figure 3). In this case a short circuit forms, leading to largely increased losses in the MOSFETs and the transformer. An estimation for the liability of a technology to the dynamic turn-on is given below.
3.3 Lowest FOMg and FOMgdThe highest demand for efficient power conversion is found in the field of dc/dc power conversion for telecom and server power supplies and similar systems. These converters are required to deliver highest currents using smallest volumes. This can be only achieved by the use of the most advanced components and topologies while operating at switching-frequencies of 250kHz and above.
For standard 48V wide-range systems, 100V MOSFETs are commonly used as primaryside switches in half- or fullbridge topologies. As switchingfrequencies are very large, a low Qg for a suitably low Rds(on) is required. The FOMG (Rds(on).Qg) is therefore a reliable measure for MOSFET selection. Additionally, the Qgd, as it directly relates to the turn-on and turn-off losses, is of equal importance.
Figure 4 shows the impact of the OptiMOS 2 100V technology on the overall efficiency of the primary side of a dc/dc converter. Note that the gained increase in overall efficiency of just 1% translates to a temperature decrease of 17°C for the MOSFET switches
[2].
Similar requirements also exist for Class-D amplifiers, where the MOSFETs are operated in half- or H-(~full-) bridge topologies.
ConclusionThe field of applications for 100V MOSFETs covers a wide range of requirements. The OptiMOS 2 100V series is a MOSFET technology that offers properties towards a safe, fast-switching and lowest-resistance single power MOSFET device.
References[1] G. Deboy, M. März, J.-P. Stengl, H. Strack, J. Tihanyi and H. Weber. A new generation of high voltage MOSFETs breaks the limit line of silicon, Proc. IEDM, 683-685, 1998.
[2] L. Goergens, D. Ahlers and J. M. Martinez Sanchez. New Opportunities in DC/DC Conversion with Recent Developments of MOSFET Technologies, Proc. EPE, Dresden, 2005.
