Robotic applications frequently include multiple stepper motors and switches. The stepper motors produce motion in several directions, and the switches identify home positions and detect proximity to obstacles. This Design Idea describes the development and implementation of a PLD (programmable-logic-device)-based interface that can connect a PC's parallel port to as many as eight switches and four stepper motors (Figure 1). This interface design serves many applications, and using IC1, a 22V10 PLD, to minimize the circuit’s component count reduces complexity, weight, and overall dimensions. Drivers IC3 through IC6 for the stepper motors comprise three L293 quad half-H- bridge ICs (Figure 2).
Each rotation of the two winding stepper motors in this design requires a sequence of four mechanical steps that you produce by applying a pair of 7V, 500mA, 120msec-long pulses to the motor’s windings (Figure 3). To make a stepper motor rotate either CW (clockwise) or CCW (counterclockwise), you apply either of two pulse sequences (Tables 1 and 2).
The following sections specify the functions of the input and output registers’ bits that control the parallel-port interface and the PLD. The PLD output-register bits are 7, 6, 5, 4, 3, 2, and 1. Q7 signals the PC that one or more switches are active. Bit 0 means that a switch is active; bit 1 means that no switches are active. With Q6, Q5,and Q4, the BSS (buffered-status switch) tells the PC which of n switches is active: 000=S1, 100=S5, 001=S2, 101=S6, 010=S3, 110=S7, 011=S4, and 111=S8. For Q3, Q2, Q1, and Q0, the PLD’s outputs enable one of the four motor-driver ICs to drive its associated stepper motor, with 1000=M3, 0010=M1, 0100=M2, and 0001=M0.
The PLD input register’s bits are E11, E10, E9, and E0. For E11, the host PC controls the PLD, 0 disables the PLD, and 1 enables the PLD. For E10 and E9, the PLD reads these lines to determine which of the four motors in Figure 2 receives drive pulses: 00 for Motor 0, 10 for Motor 2, 01 for Motor 1, and 11 for Motor 3. For bit E0, the PLD reads this bit to determine what to do with the BSS settings: 0=hold, and 1=clear. For E8 through E1, the PLD reads the status of one switch and stores it in the BSS register:
For the parallel-port output register, address 88810, D7, and D6, the PC tells the PLD which motor should run, with 00 for Motor 0, 10 for Motor 2, 01 for Motor 1, and 11 for Motor 3. For D5, the PC takes control of the PLD chip: 0 disables the PLD, and 1 enables the PLD. For D4, the PC commands the PLD to control the BSS register’s contents, with 0 for hold and 1 for clear. For D3 through D0, the PC selects which pair of motor windings get energized: 1001=A and D, 1100=C and D, 0011=A and B, and 0110=C and B. Parallel-port input-register, address 88810+1 indicates acknowledge, busy, paper, or select. The PC reads acknowledge to determine whether a switch is active: 0 means that any switch is active, and 1 means that no switch is active. The PC reads the busy, paper, or select register to determine which of the switches is active:
You can download Listing 1 for this Design Idea. Note that the PC’s portion of the software is written in Pascal, and the PLD’s internal software is written in an emulated version of Basic.
