Taiwan Semiconductor Manufacturing Company (TSMC) announced that the company has fully qualified its 65-nanometer (nm) low power process technology. The announcement officially opens the doors for TSMC to deliver the production-ready 65nm process.
Dr. Rick Tsai, president and chief executive officer, TSMC, said, "TSMC again leads the industry in pushing Moore's law to the 65 nanometer (nm) generation. At 65nm geometries, we can produce highly integrated, very small and low power devices for every conceivable market. Producing on our advanced 300mm wafers, we can ramp customers' design to high volume quickly. It provides unprecedented opportunities for customers to further advance the leadership positions in their marketplaces."
TSMC's 65nm Nexsys(SM) technology is the company's third-generation semiconductor process employing both copper interconnects and low-k dielectrics. It is a 9-layer metal process with core voltages of 1.0 or 1.2 volts, and I/O voltages of 1.8, 2.5 or 3.3 volts. The new technology offering supports a standard cell gate density twice that of TSMC's 90nm Nexsys(SM) process. It also features competitive 6T SRAM and 1T embedded DRAM memory cell sizes. In addition, this technology offering includes mixed signal and radio frequency functionality to support analog and wireless design, embedded high density memory to support integration of logic and memory, and electrical fuse to support customer encryption needs.
TSMC
