The chip-package-board codesign is emerging as a strong challenge for design engineers. ITRS has of late been calling for developing and improving codesign.
The chip and package designs have traditionally been two separate phenomena. This separation is encountering more and more problems with the integration density and clock speed rising rapidly. There are increasing instances of customers demanding that IC designers and ASIC houses design to specific pinout configurations to enable design fit on the PC board.
Greater complexity of chips arising with increasing number of I/Os and power connections, and increasing number of SiPs, multichip modules and stack dies are driving towards codesign. SiPs, though branded as poor man’s SoC, are rapidly replacing SoCs in niche applications for fast-moving markets, especially where mixed signals are not required on a single die. SiP growth will be an important factor contributing to codesign.
Collective responsibility Beyond chip-package-board codesign, what needs to be optimized is not the chip or the package or the board but the system. This makes chip-package board concept important from system perspective as well, necessitating designers to design chip-package-board as a part of the design planning for the die. The IC design group, the package-design group and the system-design group are all individually and collectively responsible to take the concept of codesign to its fruition.
I for one would have expected the thrust for codesign to come from EDA companies. However, the real thrust came from TSMC, when it released in 2004 Version 5.0 of its reference design flow, which included capability for integrating chip design and package design, using tools from EDA and other vendors. The reasons proffered for this change to the new design paradigm were given as timing and substrate routing challenges, but it seems I/O and power planning were important reasons too.
Currently most designs are at 130nm node. However, with the number of designs at 90nm and lower nodes on the rise, power is emerging a major factor driving towards codesign. At lower nodes chips are designed with such low supply voltages that IR drops have to be factored into the chip design. Reducing power dissipation and increasing battery life can be achieved by designing the package power planes to match the chip’s needs. Such matching is best obtained by codesign.
Beyond thermal issues, the signal speed at short cycle clock times is also forcing designers on the path of codesign. Signals sent simultaneously can reach respective I/O pads at slightly different times. Signal integrity can get affected. These issues are forcing companies to employ signal integrity specialists, who check signals for distortion through the die, package and board. Codesign can allow designers to compensate for many of the signal aberrations at high speed. EDA players, including the big ones such as Cadence, Synopsys and Magma, are acquiring capabilities for codesign.
Emerging concepts Some emerging concepts are that it is not necessary for all chips, packages and boards in a system to be designed from scratch in every system design; that interconnection is likely to determine the cost and performance of electronic systems at every level on the chip, in the package, and on the board; and that prototyping will become costlier at every level in the system.
Sigrity, Inc. claims that its CoDesign Studio is the only EDA solution that simultaneously co-simulates the complete chip and the entire package in an integrate design environment, identifying all distributed package effects that impact the correct operation of the chip to ensure ICs work as expected when placed into actual packages. Cadence Allegro Package SI 620 and Synopsys JupiterIO are important products enhancing codesign. Start-up Rio Design Automation’s RioMagic is a new entrant. Start-ups launching codesign products is a good market indicator.
