Most of today’s CPLDs (complex programmable-logic devices) feature reduced-power operating modes, but, when the system is not in use, a complete shutdown that conserves battery power remains the ultimate power reduction goal of many designers.
Figure 1 shows how you can add a few discrete components to a CPLD—in this example, an Altera EPM570-T100—to implement a battery-powered system’s power down circuit. An external P-channel MOSFET, Q1, an International Rectifier (
www.irf.com) IRLML6302 or equivalent, serves as a power control switch for the CPLD, IC1, and other components in the system. The CPLD and an array of switches control the MOSFET’s gate, applying bias that switches on Q1 whenever a user presses a switch. The CPLD includes an embedded timer that monitors switches and system activity. After a specified period of inactivity, the timer disables the MOSFET’s gate drive, powering down the CPLD and other components connected to the MOSFET.
Q1’s source connects to the battery’s positive terminal, and its drain connects to IC1’s VCC(INT), VCC(IO1), and VCC(IO2) power pins and other components that require power-down control. When power switches off, a 1kΩ pullup resistor, R3, keeps Q1 off by maintaining its gate at a gate-to-source voltage of 0V. When you turn off IC1, it presents a leakage path to ground through the CPLD’s power-down pin. The EPM570-T100 includes hot-socket protection that limits the current available from any useraccessible device-I/O pin to less than 300μA. Thus, even in the worst case, the voltage that the I/O pin develops across R3 doesn’t reach the FET’s minimum gatethreshold turn-on voltage of 0.7V.
Pressing any switch creates a current path through the switch’s contacts and its associated diode, which in turn develops approximately 2.3V of gate-source bias across R3—more than enough to turn on Q1 and to power up IC1 in approximately 100μsec. When you actuate the mechanical switches, they exhibit a minimum on-time of at least 3msec, whereas a typical human operator’s minimum press-and-release operation consumes at least 30msec. During these relatively slow response times, the CPLD can turn on, resetting its internal circuitry and asserting its power-down pin to a logic zero that turns on Q1 before
the operator can release the switch.
In addition to user-specified application logic (not shown), the CPLD’s power-control logic adds a pair of standard parameterized, library-macro circuits that Altera’s (
www.altera.com) Quartus II development tools generate. An internal 4.4MHz ±25% oscillator, Altufm_osc, drives a modulo-44-million LPM (library-parameterized module) counter. A logic-low signal that the CPLD’s application logic produces or closing any switch resets the counter. When you reset the counter, its carry-out signal goes low and drives the external power-down pin. An inverted version of the carry-out signal re-enables the LPM counter once you remove the reset.
If you leave all switches open and the application logic becomes inactive, the counter counts to 44 million in approximately 10 sec, and the internal carry-out signal goes high, disabling the counter and holding the carry-out signal high. In turn, the power-down pin rises toward VCC, turning off Q1 when the voltage on the power-down pin reaches 2.3V. Removing power from the CPLD places the power-down pin in the tristate, or disconnected, mode, and R3 keeps Q1 off.
You can use JTAG-compliant commands to configure the EPM570-T100 with a download cable you connect to a manufacturer-defined 10-pin header. The process requires that you press an external switch before, during, and shortly after configuration to ensure that the CPLD receives power throughout the configuration process. You can set the inactivity time-out to any desired value by changing the counter’s modulus. Although power, ground, and JTAG signals use specific device pins, you can assign any general-purpose CPLD I/O pins as inputs for switches and as the power-down output.
If your application requires a matrix of pushbutton switches, you can use only n diodes to configure an n m switch matrix for efficient power-up detection (
Figure 2). In this example, rows of switches connect to the MOSFET’s gate through diodes D1 through D4. Resistors R8 through R11 provide a ground path for each column of switches and carry current only during key closures, holding the column inputs low while waiting to minimize power-supply current drain.
When a user presses any switch, Q1’s gate goes low, turning on the CPLD. A fast CPLD-powerup routine allows the application to scan the switch matrix’s rows and columns and determine which switch a user pressed before the user can release the switch. In this application, the row signals reset the LPM counter’s inactivity timer.
