"Moving from 90 to 65nm brings significant benefits to the customer"
( 01 Sep 2006 )
by Denice Cabel, Editor, EDNAsia Online
Per Holmberg, Worldwide Director of Programmable Digital Systems Marketing at Xilinx Inc., provided insights to EDNAsia on moving from 90 to 65nm. Excerpts:
How important is being the first to come out with a 65nm FPGA solution? Per Holmberg: Moving from 90 to 65nm brings significant benefits to the customer in terms of higher performance, lower power consumption and better integration, which ultimately reduces system cost. Our studies and engagement with customers show that these are all top-of-the-list requirements for high-end FPGA designers of wired and wireless communication infrastructure, storage and servers, video and imaging, and aero/defense applications. In comparison with Virtex-4, Virtex-5 (the world’s first 65nm FPGA) provides 30 percent higher performance, 35 percent lower dynamic power (comparable static power), and 65 percent more logic. By being first to market a high performance FPGA family in the 65nm process node, we can offer all these benefits to the customers before our competitors.
How does your 6-input LUT approach work and how will customers benefit from it? P.H: To meet customers’ increasing need for higher performance and lower power, we have to innovate on an architecture level. There are two main areas where this can be done—more efficient logic implementation through an enhanced lookup table (LUT) structure, and faster connectivity through an improved interconnect architecture. We have addressed both areas with our new ExpressFabric architecture. This includes a LUT with six independent inputs, making it a true 6-input lookup table. Equally important is the improved diagonal interconnects structure in Virtex-5, which enables the tools to connect neighboring LUTs with fewer hops.
What are the hot R&D topics for Xilinx? P.H: Meeting designers’ appetite for higher performance, lower power, higher integration, and lower cost on a system level continues to be a hot R&D topic. It entails more-than better architectures and technology nodes. New innovations are required such as triple-oxide technology to reduce power consumption, sparse chevron packaging to improve signal integrity, and ChipSync to improve bandwidth and reliability for high-speed memory interfaces, among others.
What is your biggest challenge today? P.H: We see a great opportunity to rapidly grow the FPGA market by expanding into high-performance DSP, embedded processing, and programmable system domains. By targeting these additional segments, the total available market for FPGA usage will grow tremendously. To meet the requirements of these new domains, we provide multiple domain optimized FPGA platforms with hardened and soft IP, new development tools, and design methodologies.
One of the bigger challenges we face with this strategy, and an area where we’re investing heavily, is to provide design solutions that are compatible with the needs of this new customer base. For example, DSP designers are designing in terms of sample rate, MAC, etc., and they use design tools from The MathWorks or code in C. They’re not necessarily familiar with VHDL or Verilog, and they are not used to synthesis and floor planning tools. To help these designers successfully take advantage of FPGAs, we provide DSP design tools such as the System Generator for DSP, and AccelDSP tools integrated in the already familiar MATLAB and Simulink tools from The Math-Works. Evangelizing FPGAs for these new application domains is a top priority for Xilinx.
