Texas Instruments' 45nanometer (nm) semiconductor-manufacturing process leverages a "wet" lithography process to double the number of chips produced on each silicon wafer, increase processing performance, and reduce power consumption.
According to the company, these techniques will drive the capabilities of its multi-million transistor, SoC processors to new levels, increasing performance by 30% while reducing power consumption 40%.
TI estimates that its 45nm process and SoC integration capabilities will mean consumers can experience up to a 30% improvement in device speed, which can translate to more video frames per second for a better user experience on mobile phones. In addition, wireless users will be able to run more simultaneous applications such as a game with 3D graphics in parallel to a video conference between the players, with e-mail synchronizing in the background.
TI's 45nm process leverages SmartRef lex power and performance management technologies that combine intelligent and adaptive silicon, circuit design, and software to address power management challenges. The process also supports DRP architecture to integrate digital RF functionality in single-chip wireless solutions. This SoC approach to wireless transmit and receive functions allows TI to apply its highly efficient CMOS manufacturing infrastructure to reduce overall system cost, reduce power consumption and free up board space.
Texas Instruments Incorporated www.ti.com
