Throughout the advances till 90nm process node, designers could anticipate the difficulties at the next node before reaching the node. The jump from 90nm to 65nm seems different. Designers are not clear whether they should move in the same direction as before, or they should take an altogether different direction for success. This confusion persists even as IBM, Chartered, Infineon, and Samsung collaboration has announced the first 45nm design kits.
PERFORMANCE INDEX The discontinuation of clock cycle as microprocessor performance index means that designers are trading off speed for gates. There are more gates to build parallel systems that perform the same tasks at lower speed. Should the designer get higher performance through higher clock speed or through using more gates? The right answer seems to be blurred by the fact that technology refuses to remain stagnant. In the 1990s, designers were designing chips with say 100,000 gates; today, at the leading edge, with 100 million gates, making tremendous difference in design. Earlier, they were designing a component for a system; today, they are designing the system itself. Earlier, design methodology was RTL; today, it is ESL, requiring a designer to have a wide range of both hardware and software experience. Earlier, the designer would tape out the design himself and ship it to foundry; today, at 90nm, the design has to be accompanied by process and product engineers for a reasonable chance of success.
At 65nm, even this does not work with surety. Nobody seems to know what would work. One scenario emerging is that no set of rules will always be successful. One set of rules that succeeds for a particular design does not succeed for another design. Foundry engineers find new kinds of problems in each new design, and create new rules to solve them. The list of rules is becoming so unwieldy that the rules themselves are becoming a hindrance to design success. Designers are finding that the voluminous amount of rules make checking for compliance impractical. Some feel that too great compliance nullify the supposed advantage of leading-edge process nodes. Some find that with plethora of rules, building design blocks becomes impracticable. Now some designers are looking at a design world beyond rules. While they take in data from rule checkers and analysis tools, they use the data only as a supplement to their own design skills based on experience.
I think TSMC has taken an important step towards reducing the cacophony. For its 65nm reference flow, TSMC has created a common data format for its eight DFM partners included in the flow. This common data format provides the chip designer with critical-area analysis, lithography-process checking, and virtual-CMP modeling. Later the format will provide parametric modeling too. The format will not enable the designer to know the yield, but it can predict lithography and CMP hot spots in the design, enabling tools to flag areas that might contain errors.
MODEL-BASED EDA TOOLS EDA continues to grapple with the problem. In the pre-65nm era, it built abstract models of only those processes whose variations designers knew. But at 65nm there are an estimated 2,000 to 3,000 sources of variations. EDA companies are switching to tools that use models to encapsulate these complex effects. However, will it be possible for EDA tools to model such a large number of variations?
Mentor Graphics’ Calibre nm, the latest version of its design platform, and Calibre nmDRC, a design rule checker aimed at handling escalating design complexity, are a step from rulebased to model-based approach. It remains to be seen to what extent it can model the proliferating process variations. Its success will ameliorate the growing criticism against the EDA industry that it has not kept pace with process advancement to offer the right tools.
