Extensions to the IEEE 1149.1 boundary-scan standard

The IEEE 1149.1 boundaryscan standard was developed almost 15 years ago to resolve the problems associated with limited physical access for probing test points on printed circuit boards (PCBs), to verify that device pins have been soldered correctly and are free of solder shorts and open circuits. However, the test industry now faces new problems that were not envisaged when the 1149.1 standard was developed back in 1990, and there has been a sustained effort by a number of working groups to develop new standards that build on the success and acceptance of the IEEE 1149.1 standard.

IEEE 1149.4 STANDARD
The 1149.4 standard specifies that every signal pin must be associated with a boundary module, which in the case of the digital pins is referred to as a digital boundary module (DBM) and are identical to boundary-scan cells defined within the 1149.1 standard. In the case of mixed-signal pins, these will be associated with analog boundary modules (ABM) consisting of a switching network connected between the pin and the core circuitry, allowing the pin to be put into the core disconnect (CD) state, which will isolate it from the core and allow it to be connected to either an external signal connected to that pin, an internal dc voltage, or the internal analog test bus¹.
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The IEEE 1149.1 boundaryscan standard was developed almost 15 years ago to resolve the problems associated with limited physical access for probing test points on printed circuit boards (PCBs), to verify that device pins have been soldered correctly and are free of solder shorts and open circuits. However, the test industry now faces new problems that were not envisaged when the 1149.1 standard was developed back in 1990, and there has been a sustained effort by a number of working groups to develop new standards that build on the success and acceptance of the IEEE 1149.1 standard.

IEEE 1149.4 STANDARD
The 1149.4 standard specifies that every signal pin must be associated with a boundary module, which in the case of the digital pins is referred to as a digital boundary module (DBM) and are identical to boundary-scan cells defined within the 1149.1 standard. In the case of mixed-signal pins, these will be associated with analog boundary modules (ABM) consisting of a switching network connected between the pin and the core circuitry, allowing the pin to be put into the core disconnect (CD) state, which will isolate it from the core and allow it to be connected to either an external signal connected to that pin, an internal dc voltage, or the internal analog test bus¹.

Although the IEEE 1149.4 standard. was approved in June 1999, the industry has been very slow in adopting the standard and more importantly, for silicon vendors to produce devices that would enable board designers to utilize and experiment with the technology.

In order to stimulate some interest in the implementation of the 1149.4 standard within the industry, National Semiconductor2, an innovator in analog semiconductor markets, and LogicVision, a leading provider of embedded test for integrated circuits and systems, collaborated in developing the first generalpurpose, IEEE 1149.4-compliant integrated circuit (IC) called the STA400 detailed in Figure 1.

This was primarily an evaluation chip with minimal core functionality, other than that of a simple analog multiplexer, which comprises eleven ABMs that can be connected to circuit nodes to enable the injection of a test stimulus or the monitoring of discrete dc voltages and ac-signals.

The value of discrete passive components can be determined by injecting a current source to different signal nodes, measure the resultant voltage potential at each node and by a simple calculation using "Ohms Law" deduce the value of the selected passive component.

JTAG Technologies have developed an 1149.4 evaluation kit that utilizes the STA400 devices to enable users to select circuit nodes and perform resistance, capacitance, voltage, ac-signal or characteristic impedance measurements on an evaluation board using a graphical user interface.

In another application of the evaluation system, users can perform analog measurements on their own target board designs by using the test resources (stimulus and measurement instrumentation) of the JTAG-149.4 Explorer3. Further information can be obtained from IEEE 1149.4 Working Group Web site.⁴

LEVEL OF STANDARDIZATION
For many years the test industry has been asking for some level of standardization for the insystem configuration (ISC) of programmable devices. In the past, suppliers of programmable silicon have used different programming algorithms, not only between vendors, but also between different families of devices from the same vendor.

The silicon portion of the standard establishes common device behavior during programming via the IEEE 1149.1 state machine. The software portion of the standard defines a modified boundary-scan description language (BSDL) file, which has been extended to cover the new ISC instructions.

Additionally, there is a new ISC data file, which contains all the device and pattern-specific programming information.

The in-system configuration features of 1532 compliant silicon will deliver significant savings to the manufacturing community by delivering faster programming times and facilitating a more efficient use of expensive testers. Users will now be able to program chains of cPLD's from multiple vendors using the same third party programming tools and controllers.

Users will no longer require vendor-specific programming knowledge, whilst multiple programmable logic devices from different silicon vendors can be programmed concurrently. By programming devices concurrently instead of sequentially, all devices enter and leave the programming wait states simultaneously, significantly reducing the overall programming time. This allows end users to select programmable devices according to their design needs, whilst still minimizing configuration time.

Reference

1. Analog and Mixed-Signal Boundary-Scan: A Guide to the IEEE 1149.4 Test Standard, edited by Adam Osseiran, Kluwer Academic Publications 1999.

2. National Semiconductor, STA400, 1149.4 Evaluation Device http://www.national/com/appinfo/scan/

3. JTAG-1149.4 Explorer Mixed-Signal Boundary-Scan Evaluation System; http://www.jtag.com/

4. IEEE 1149.4 Mixed-Signal Test Bus Working Group http://grouper.ieee.org/groups/1149/4/index.html