To produce trains of pulses suitable for keying transmitters, testing circuits, and debugging data links, designers requiring continuous or event-driven pulse sequences have traditionally relied on pulse generators or collections of simple circuits. Today's inexpensive microprocessors make it possible to design and build lowcost, dedicated pulse-sequence generators with a minimum of resources. In a small, SOT-23- packaged, 10F200 controller from Microchip, the design in Figure 1 uses a code-based embedded table algorithm to generate an application-settable period and table-based PWM (pulse-widthmodulation) sequence. The application produces a continuously pulsed sequence and requires only three constants and a pulse-width profile table that it copies into the microprocessor's assembler-based code before compiling (Figure 2).
All code branches undergo equalization to produce a group of 29 constant instruction times. During software development, you can use coded constants and a table-based approach as a flexible method of modifying the pulse sequence. The three parameters that Figure 2 highlights include the number of PWM cycles that execute between tabled steps, which the algorithm passes as "temp_cntK." This parameter defines how many PWM periods of a range from one to 255 repeat within each tabled step. For three cycles per table step, you use #define temp_cntK .3. The next parameter is the number of 29- instruction loops that execute during each PWM period. All branches of the coded instructions equalize to constant 29-instruction periods. When you copy this parameter as "loopsK," it can range from one to 255. Using the 10F200's internal 4MHz clock and an 8-bit counter to generate 1μsec instruction periods, you can generate a PWM period range of 58 to 7395μsec, which corresponds to a frequency range of 17,241 to 135Hz. For a 1msec PWM-cycle period and the sequence in Figure 2, you require 31 base loops per cycle, which you obtain by dividing 1 msec by the 29μsec instruction period: #define loopsK .31.
You then equate the total number of table profile steps to "table_maxK." The total number of profile steps that a look-up table includes and that you copy into the code may vary from one to 252. In this application, five tabled steps correspond to pulse duty cycles of 25, 50, 87.5, 12.5, and 75%. These values undergo scaling according to the following equation: Duty cycle=INT(%TDTY/100_loopsK+0. 5), in which INT is the integer value and %TDTY is the percentage of the total duty cycle. In this example, loopsK=31. The number of steps in the table passes to the program as #define loop_maxK .5.
The pulse-duty cycle can vary only in increments of a single 29- instruction base loop, and, as a consequence, the pulse duty cycle's resolution varies as the number of basic loops for the waveform's desired period, which you define as loopsK=31 loops. Thus, the dutycycle resolution equals 1/(loopsK), or 1/(31)=3.22% for this application.
You can use a spreadsheet or manually calculate the translated and scaled duty-cycle values and store them in the data-profile table. For example, you calculate the value for a 25% duty cycle as INT(25/resolution+0.5)=INT(25/3.2 2+0.5), where INT represents extraction of the integer value of the computed quantity. For required duty cycles of 25, 50, 87.5, 12.5, and 75%, the values that pass to the data-profile table are retlw_8, 16, 27, 4, and 23, respectively. The assembly-language program includes these duty-cycle values and the three other parameters.
The program includes two additional features: Connecting Pin 1 to ground enables a continuousoutput mode. Connecting Pin 1 to +VDD evokes a single output waveform. Pin 3 serves as a high true-output enable when you connect it to +VDD or as a positiveedge trigger input when you pull the pin to ground and release it. Note that the program currently includes no contact-debounce routines for either input.
In the example in Figure 3, the controller delivers a pulse-widthmodulated output (lower trace), which, after processing by a singlepole lowpass filter, corresponds to a sine wave (upper trace). Using another version of the circuit, you can evaluate how a critical midword error affects a serial link's characteristics, system timing, and response latency.
The waveform in Figure 4 comprises 100 pulses, 99 of which exhibit a nominal duty cycle that varies from 48 to 51%, and a single error pulse with a 75% duty cycle. The waveform-table entries use values of loopsK=100, temp_cntK= 1, and table_maxK= 100 to produce a pulse sequence comprising 74 pulses with nominal duty cycles, a single pulse with a 75% duty cycle, and a final sequence of 25 clocks with nominal duty cycles. The entire sequence repeats at a 345Hz rate.
Using a 4MHz-clock-rate version of Microchip's 10F220 controller constrains the basic software-timing loop to a 29μsec period. You can compile the program into an 8MHz 10F220 to reduce the timing loop to 14.5μsec and extend the output's usable bandwidth. You can modify the code in the listing to suit other compatible microprocessors to obtain greater bandwidth and integrate additional functions. As is, the circuit requires only 155bytes of internal EEPROM and occupies an SOT-23 pc-board footprint-not bad for a processor that costs less than $1.
