Ultralow-cost, two-digit counter features few components
( 01 Dec 2006 )
Noureddine Benabadji, University of Sciences and Technology, Oran, Algeria
The ultralow-cost, twodigit- counter circuit in Figure 1 represents an attempt to reduce the number of components using a mostly software approach and a low-cost microcontroller, the PIC16F84A. The circuit lacks the current-limiting resistors that normally connect to a sevensegment LED display’s pins because a software routine lights only one of the display’s segments at a time, first in the 10s display and then in the units display. Doing so keeps the circuit’s maximum current consumption at a nearly constant level, even if you add a third LED display to implement a three-digit counter. The circuit also lacks digitselection switching transistors that classic multiplexed circuits’ switching transistors typically use, and the circuit includes one common-cathode and one common-anode display. The reason for this approach is that each of the microprocessor’s I/O Port A and Port B lines can assume one of three states: high, low, and floating—that is, high impedance. Programming a line as an input places it in a high-impedance state, which turns the display off.
In addition, the program drives only one segment at a time and executes the following sequence: To drive the 10s display, program the line RB0 output and drive it high to light the corresponding segment of the common-cathode display and then program RB0 as an input. Repeat this procedure for lines RB1 through RB6. To drive the units display, repeat the process while applying a low output from RB0 to drive the common-anode display. Figure 2 shows the circuit’s timing diagram. The prototype display uses Kingbright’s (www.kingbright. com) SC52-11EWA (DS1) and SA52- 11EWA (DS2) high-efficiency, seven design segment displays that emit 2000 to 5600μcd at a forward current of 10mA. At a forward current of approximately 5mA, the displays remain readable.
Early motion pictures displayed at an 18Hz rate, which produces marginal f licker. The software executes at a rate of 180Hz, or 10 times the minimum flicker rate. Each of the display’s seven segments must illuminate for an interval of 1/(1807) sec, or approximately 0.8msec. To simplify the timing routine (section Delay3 of Listing 1, available at www.edn. com/060817di1), the software uses a refresh interval of 1msec.
Although this approach provides adequate segment-drive current, the display’s internal LEDs carry a 3V maximum reversevoltage rating. Driving any I/O line high applies forward bias to one segment of the common-cathode digit but applies reverse bias to the corresponding segment of the common-anode display. The 16F84A requires a minimum of 2V for operation, and thus the circuit must operate in a 2 to 3V power-supply range. The assembler source code in Listing 1 counts from 0 to 99sec and serves as an unoptimized proofof- concept software test bed for the display.
