IMEC has developed a reconfigurable processor for video decoding achieving power efficiencies 6 to 12 times higher than state-of-the-art C-programmed processors. The processor derived from IMEC's C-programmable ADRES (Architecture for Dynamically Reconfigurable Embedded Systems) is using its corresponding compiler. It proves that ADRES and its compiler are well suited for time efficient integration in future low-power portable wireless multimedia devices.
The processor developed to support multi-format MPEG-2, MPEG-4 and H.264/AVC video decoding at resolutions ranging from QVGA up to D1. Its functionality is demonstrated for 30 frames per second H.264/AVC video decoding at CIF resolution by means of an FPGA (field-programmable gate array) implementation.
To decode CIF resolution video in real time, the multimedia ADRES processor is only used for 1/6 of its total capacity (50MHz), resulting in a simulated power consumption of around 17mW for an ASIC implementation. The result proves the high performance efficiency of ADRES requiring only one single ADRES processor for handling 30fps H264/AVC video decoding at for example VGA (50mW, 150MHz) and D1 (68mW, 205MHz) resolutions.
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