Multi core concept has been in the market for quite some time since its introduction. In its final phase, one would need to choose an appropriate configuration of the computing engine from various proposed configurations available, in order to achieve the system requirements including Performance, Cost, Power Consumption, Software Development Effort, OS Consideration, etc.
This session reviews how Renesas approaches the Multi Core SuperH (both SH-4A and SH-2A) development: Focusing on how Renesas’s first Dual Core SH-2A with relations to driving application features in reality. As SH-2A is a controller CPU core, with its applications in specific field, the CPU will tend to have requirements on handling pre-determined real time tasks. Recommendations on software and OS configuration will also be mentioned.
Graphical system design is a revolutionary approach to designing embedded systems.
This session reviews the innovations in engineering tools and technologies for the last 30 years and how virtual instrumentation has changed the way systems are designed, prototyped, and deployed. Find out how graphical system design and prototyping on a standardized platform approach can simplify embedded systems development.
Key benefits include:
• A graphical programming environment that delivers high-level productivity so that engineers can develop embedded systems easily
• A tight integration between hardware and software that delivers a tremendous decrease in time to first prototype
FPGA devices continue to provide increases in integration, features, and speed to support the demands of next-generation digital systems. The latest generation of high-end FPGAs offers integrated microprocessors, DSP capability, high-speed serial I/O, and levels of logic integration orders of magnitude greater than high-end FPGAs of only a few years ago. This allows system designers to achieve true system-on-chip capability in a programmable device, realizing with a single programmable chip what took an entire board (or even multiple boards) only a short time ago.
While this capability enables dramatic new contributions in systems under development, it also presents some unique challenges to today’s system designer in the debug and validation phases of the design. For example, as the complexity of the design implemented in the FPGA increases, the challenges associated with fully understanding its behavior increase dramatically, since more and more system blocks “disappear” inside the chip. An answer to these challenges is the use of on-chip debug structures that can provide insight into system behavior and help identify and correct problem more quickly. Such approaches can significantly shorten the designer’s time spent in debugging the design, which typically translates into a reduction in overall development time.
This paper will present various concepts for on-chip debug that provide insight into the detailed operation of the design implemented in the FPGA itself as well as the surrounding system in which the FPGA operates. Information describing reductions in debug and overall design time will be discussed, allowing the participant to better understand the options available and the tradeoffs associated with them.
While device software runs on top of 98% of the world's microprocessors and collectively constitutes today's largest and fastest-growing technology market, it is still arguably immature. Because devices differ so widely by form factor, vertical market, and function, companies have been slow to recognize and capitalize on the fundamental sameness of development technologies and processes. Instead, many key companies, and many development teams within those companies, have created multiple one-off, in-house solutions that don't integrate and don't scale. The resulting fragmentation produces discouraging results across the industry – 66% of projects completed behind schedule, 33% functionally unacceptable, 24% cancelled before completion.
This session reviews how the application of a disciplined methodology to the challenges of device software development, Device Software Optimization (DSO) offers a vibrant technology market the means to mature.
Microcontroller- and ASIC-based designs have traditionally dominated embedded-control systems. These designs can become overly complex from a component standpoint as new features and functionality are added. The dsPIC® Digital Signal Controllers (DSCs) from Microchip Technology solve this problem by offering several advanced peripherals on a single chip that can perform functions typically served by multiple chips. The dsPIC DSCs combine the look and feel of a traditional microcontroller with the advanced processing capabilities of a DSP, enabling increased performance, reduced component count and smaller overall designs.
To support development with the dsPIC33F DSCs, Microchip offers comprehensive peripheral-, encryption- and DSP-algorithm libraries, as well as applications-based Graphical User Interfaces (GUIs). When used in conjunction with the MPLAB® IDE, these libraries and GUIs reduce time to market, cut costs and increase productivity. In a highly competitive market, these factors provide an edge over the competition.
This presentation will discuss the feature-rich dsPIC33F family of DSCs and illustrate its capabilities using a Home Security Alarm System design example. Software libraries in support of the dsPIC33F DSCs will be demonstrated, such as those designed for soft modems and speech-processing applications. The presentation will also discuss applications beyond speech for which the dsPIC33F DSCs are appropriate.
Embedded systems are very pervasive, and the trend to integrate more functionality in devices is steadily increasing. Especially for devices in security-relevant areas such as brake systems, machine controls or aeronautics special requirements reg. The security level of the application come into play. In lockstep we see mounting requirements to the design engineers and the quality control departments to meet these requirements, and submit sufficient documentation to be certified and/or accepted by their suppliers.
In the past, and still in many companies, software testing is done individually, and manually. This bears several risks. Test data is not reusable, a new engineer is hired, the process begins anew. In case of modifications to the program, all tests have to be re-executed manually, the results noted, and the new features integrated.
In order to save time, the risk is great that the engineers will test only the new part of the program, and not how or if it affects the already tested parts.
Quality control departments are often assigned the task to oversee the testing of software, and need to develop a testing “map” in order to ensure that all eventualities are taken care of. This is very difficult if it is done manually by several different people, who then cut & paste their designs together.
Therefore, we have noted an increased interest in embedded software testing automation. It was driven first by the automotive industry, who outsource many of their systems to their suppliers, and whose reputation is build on the quality of each part.
The presentation will be on the requirements, the standards (SIL), and resulting testing possibilities and the options to automate the testing and the design of testing.
