Choosing reset usage and its strategies in ASIC/FPGA designs require many design considerations like whether every flip-flop will require a reset, whether to use a synchronous reset or asynchronous reset, how the reset tree will be structured and buffered, how to verify timing of reset tree, how test scan vectors are applied to check functionality of reset and how reset is handled in multi clock domain designs. In this article, we will see how FPGA components like shift registers, Block RAM, Distributed RAM, and DSP Slices can be used efficiently with proper use of reset.

Coding consideration for pipeline flip-flops

The designer should not mix the resettable and non-resettable flip-flops in the same Verilog procedural block or VHDL process block. The correct way to code pipeline flip-flops with two Verilog procedural blocks is shown below. These coding styles will generate the logic shown in Figure 1.

module follower_FF (Clk,Rst,d,q1); input Clk; input Rst; input d; output q1;

reg q; reg q1;

always @ (posedge Clk) begin if(Rst) begin
q <= 1'b0; end else begin q <= d; end end

always @ (posedge Clk) begin q1 <= q; end endmodule

EDNA FPGA 04 Figure 1: Follower flip-flop without reset

As shown in below code, if both the flip-flops are modelled in the same procedural block than it would generate logic shown in Figure 2. The below coding style generates extra logic by using reset signal Rst as a data enable for the second flop.

module follower_FF (Clk,Rst,d,q1); input Clk; input Rst; input d; output q1;

reg q; reg q1;

always @ (posedge Clk) begin if(Rst) begin
q <= 1'b0; end else begin q <= d; q1 <= q; end end endmodule

EDNA FPGA 05 Figure 2: Follower flip-flop with bad coding style

Reset usage in data path & control path in FPGA

Implementation of resets in FPGA are associated with the corresponding vendors. Therefore, before implementing FPGA hardware with a kind of reset, it is recommended to carefully read the FPGA vendor’s datasheet and HDL coding guidelines. Some FPGA hard macros, like SRL, DSP Blocks, BRAM Blocks, and SERDES support only limited reset options, or none at all. Therefore, resetting such logic resources incorrectly, might prevent inferring dedicated hard macros and affect the utilisation and performance by inferring LUT logic and Slices flip-flops in place. Hence, reset issues such as synchronous or asynchronous, active high or low should be decided on the basis of datasheets, and configurable logic capabilities of the corresponding FPGA.

Proper use of reset signal for these hard macros will improve performance, timing and lead to have better device utilisation. Below section summarise the usage of reset for various hard macros in FPGA.

Active High reset

Xilinx FPGA Flip-Flop has active high control port SR for preset/clear/set/reset functionality as shown in below Figure 3. The SR port will be inferred as an asynchronous preset/clear or as a synchronous set/reset depending on the type of flip-flop, the RTL code describes.

EDNA FPGA 06 Figure 3: Flip-flop control signals

Active low usage of preset/clear/set/reset functionality in RTL code will require an inverter before the flip-flop to drive the active high SR port. This inverter will be inferred in the LUT affecting the timing, power and device utilisation.

If somehow we can not control the polarity of external signal and it still uses the active low polarity, then it is recommended to invert the active low reset signal in top level hierarchy and then route that signal to all other registers. This will infer the inverter into IO logic and no additional FPGA routing or logic will be used for remaining registers.

Synchronous reset

SR control port of all the flip-flops within a slice is common. Therefore different types of flip-flops cannot be packed into the same slice. As shown in Figure 4, three flip-flops with different asynchronous control signal are used and thus they consume 3 different slices. But if the synchronous control signals were used, then the synthesis tool maps the synchronous control signals into LUT and won’t use control port of flip-flops. This will allow packing of different control signals flip-flops in the same slice. This may increase the LUT utilisation but improves the slice utilisation. Thus it’s better to use synchronous control signals in order to have better slice utiliation.

EDNA FPGA 07 Figure 4: Control set optimisation on SR

SRL Component

In Xilinx FPGA, there is a dedicated SRL component available which can be used to infer shift register functionality. SRL component uses SLICEM LUT logic to infer the shift register. If the code describes the shift register with synchronous or asynchronous reset then tool will use flip-flops for the shift register. While if shift register is coded without reset then the tool will infer the dedicated SRLs within the slices. Thus for better device utilisation it is advisable not to use resets for inferring the shift registers in the hardware.

Below is Verilog code written with reset which will infer flip-flops for shift register.

always @ (posedge Clk or posedge Rst) begin if(Rst) begin q <= 0; end else begin q <= {q[6:0],Din}; end end

assign q1 = q[7];

But if code is written without reset as shown below then dedicated SRL components will be inferred.

always @ (posedge Clk) begin q <= {q[6:0],Din}; end

assign q1 = q[7];


There are two types of RAM provided in Xilinx FPGA. One is dedicated Block RAM and second is distributed RAM inferred within CLB LUTs. An explicit reset cannot be used to reset the content of the RAMs. Thus while writing a code intended to infer the RAMs, one should code without reset.

The type of RAM inferred from the code depends on the type of read coded for the RAM. If the read is synchronous then BRAMs are inferred while if read is asynchronous then Distributed LUT RAMs are inferred.

The below coding style with asynchronous read will infer Distributed RAM Macro in RTL.

//Dual-Port RAM With Asynchronous Read Verilog Coding Example

module rams_00 (clk, we, a, dpra, di, spo, dpo); input clk; input we; input [5:0] a; input [5:0] dpra; input [15:0] di; output [15:0] spo; output [15:0] dpo;

reg [15:0] ram [63:0];

always @(posedge clk) begin if(we) begin ram[a] <= di; end end assign spo = ram[a]; assign dpo = ram[dpra]; endmodule

Below coding style with synchronous read will infer Block RAM Macro in RTL.

// Dual-Port RAM with Synchronous Read (Read Through) module rams_01 (clk, we, a, dpra, di, spo, dpo) input clk; input we; input [5:0] a; input [5:0] dpra; input [15:0] di; output [15:0] spo; output [15:0] dpo;

reg [15:0] ram [63:0]; reg [5:0] read_a; reg [5:0] read_dpra;

always @(posedge clk) begin if(we) begin ram[a] <= di; end read_a <= a; read_dpra <= dpra; end assign spo = ram[read_a]; assign dpo = ram[read_dpra]; endmodule

Xilinx BRAM contains output register primitive at the data output. To utilise that register in BRAM, One must use the synchronous reset in BRAM. Otherwise it will not use that dedicated output register and use flip-flop from a CLB.

DSP Slices

DSP48 slices are available in Xilinx FPGA to accelerate DSP algorithms and solve complex DSP challenges. DSP48 Slices have pipeline registers both in control and data path to enhance the performance of the design. All these DSP48 internal registers have a synchronous reset. So if asynchronous reset is used in coding then the synthesis tool won’t be able to pack these into DSP48 block and would require the additional CLB registers to implement the asynchronous reset functionality. This not only leads to poor device utilisation but also impacts performance and power. Therefore it is recommended to use synchronous reset to infer the internal registers of DSP48 slices for improved performance.


The flip-flops in the control path should have reset to bring the digital system to a known state, while one can do without reset for flip-flops in data path. As a rule, all the flip-flops that receive their state through feedback should have reset. However, flip-flops that are pipelined or follower flip-flops, or updated with some valid logic, do not need reset. Optimal usage of reset in designs leads to improved logic, timing, power and routing.

Implementation of resets in an FPGA is dependent on the vendor. Hence, reset types or their usage for the hard macro should be decided on the basis of the corresponding FPGA vendor datasheet and their configurable logic capabilities. The recommendation and guidelines provided here will help designers choose the appropriate reset type and usage in their designs.

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