A typical industrial and consumer application is a system that samples an environmental condition, such as GPS (global-positioning-system) location, voltage, temperature, or light, at a wide interval, such as once every minute. This type of system is becoming increasingly wireless and battery-powered; it wakes up every minute, takes a sample, transmits data to a central data-collection terminal, and then goes back to sleep. This design idea uses a small portion of an Altera EPM240-T100 CPLD (complex programmable-logic device) with a few discrete capacitors, resistors, diodes, and MOSFETs to autonomously wake a CPLD-based system from a full power-down state to an on state using an RC-timer circuit. This approach results in minimal power consumption during samples when the power is on and between samples when the system, except for the RC circuit, is effectively off. Figure 1 shows the basic CPLD on/off timer. Q1, an IRLML6302 P-channel MOSFET, is the power-control switch for the system. When the gate node is at VCC, which R2 pulls up, the power to the CPLD and the entire system is off, leaving only the RC circuit to use a minute amount of power. The CPLD comprises a control block, a 4.4MHz internal oscillator, a 3bit register, and six I/Os.

EDNAOL 2016JUN13 AN 01Fig1Figure 1: The CPLD comprises a control block, a 4.4-MHz internal oscillator, a 3-bit register, and six I/Os.

Figure 2 shows the state machine of the control block. The outputs in the state box are high, and all others are low. The dashed line from power-down to power-up represents the time delay, which the RC circuit comprising R1 and C1 measures when the system is off. Switch S1 turns on and initializes the circuit. When S1 closes, D2 drives the gate node low, consequently turning on Q1 when the gate voltage is 0.7V below VCC. The EPM240-T100 is then operating in the power-up state less than 200µsec after Q1 applies power. The power-up state drives the power node low, which holds the gate voltage at 0.7V, keeping Q1 on after the switch is open. The power-up state also drives the charge node to VCC. This action charges the negative terminal of C1 to VCC. Because reset=0, the control block goes to the reset state and Register 1 gets reset. Once S1 opens, the control block goes to the enable state and drives the enable signal to one. EDNAOL 2016JUN13 AN 01Fig2Figure 2: In the state machine of the control block, the outputs in the state box are high, and all others are low. The sample-and-transmit circuit then begins operation and drives the done signal to zero. Once the sample and transmit are complete, the done signal becomes one, and the control block goes to the save state. The save state charges capacitors C2 to CN based on the value in Register 1. The save state is active for 100µsec, allowing the outputs to fully charge the 10-µF capacitors. After 100µsec, the control block goes to the power-down state, which stops driving the charge and power nodes. R4 pulls the power node high, leaving R2 to pull up the gate node. Once the gate node reaches VCC–VTQ1 at about 2.3V, Q1 shuts off power to the system. All EPM240-T100 I/O is in a high-impedance state and does not affect the gate or charge nodes. The charge node starts at VCC and begins to discharge through R1 once power is off. Once the charge node drops to 2.3V, D1 pulls down the gate node. Once the charge node reaches 1.6V, the gate node reaches 2.3V, and Q1 turns on. The time for Q1 to turn on is slightly less than the τ of R1 and C1. Off time equals R1×C1=100,000×0.0001=10 sec. The device powers up in the power-up state but moves quickly to the sample state. The sample state reads the value on capacitors C2, C3, and C4. These capacitors act as nonvolatile memory, storing the count of previous power cycles. If the Register 1 value sampled on C2 through C4 is less than 7, then the control block goes to increment, and the Register 1 value increments by one. Then, the control block again goes to the save state to charge C2 through C4 to a new binary value, 001. The device powers down again. On the eighth power cycle, or about 80 seconds after power-up, the control block moves to the enable state, thus enabling a new sample-and-transmit sequence. This process repeats every 80 seconds. You can change the period by adjusting C1 and R1 and by changing the Register 1 size and count between enable cycles. Based on an 80-second period comprising eight smaller power-up samples, test, and power-down cycles, the duty cycle for power is less than 3%; therefore, this approach increases battery life by as much as 33 times.
This article is a Design Idea selected for re-publication by the editors. It was first published on April 12, 2007 in EDN.com.