Signal processing IP licensor CEVA has unveiled the CEVA-X2 DSP, a small and highly-efficient processor specifically developed to tackle the enormous PHY control complexity of multi-carrier, multi-standard modem designs for LTE-Advanced Pro and 5G smartphones.

The CEVA-X2 combines powerful DSP performance with efficient control capabilities such as reduced code size and cycle count and with advanced system control features such as multi-processor support with cache coherency and automated hardware acceleration management.

For advanced modem workloads where the emphasis of the DSP is PHY control processing—for example, where the PHY Datapath tasks such as per-channel measurement and decoding are not required to run on the DSP—the CEVA-X2 offers a 30%-65% better die size efficiency and 10%-25% better power efficiency compared to CEVA-X4 DSP. The CEVA-X2 is also ideal to run both the PHY and MAC for a range of other communication standards, including IEEE 802.15.4g, ZigBee, Thread and power line communications (PLC), combining power efficiency with minimal die area for such use cases.

“The NEW CEVA-X architecture framework addresses the DSP ‘design gap’ that exists for companies developing next-generation modems, including those targeting LTE-Advanced Pro and 5G. Many existing DSP architectures simply don’t have the performance to tackle these advanced use cases efficiently," said Michael Boukaya, VP and GM, wireless business unit at CEVA.

The CEVA-X2 features a 64-bit SIMD data path and support for five-way VLIW instructions, together with a 10-stage pipeline and support for both fixed- and floating-point operations. The DSP is equipped with high-end features to compete with the best off-the-shelf controllers, including a dedicated 32-bit zero-latency Instruction Set Architecture (ISA), 32-bit hardware division and multiplication, dynamic branch prediction and ultra-fast context switching.