Semiconductor solutions provider Renesas Electronics has presented an embedded SRAM circuit, which the company said has a standby power of 13.7nW per Mbit and 1.84ns readout.

The company applied its in-house 65nm node silicon on thin buried oxide (SOTB) manufacturing process for the prototype development of the embedded SRAM. The SRAM takes advantage of the SOTB structure by using dynamic substrate back bias control to achieve a low standby-mode power consumption, which is one-thousandth of the power consumption during normal standby mode.

The ability to significantly reduce standby power while still retaining data in SRAM is expected to extend battery life for IoT, home electronics and healthcare applications. It may also allow for no battery operation natural energy sources such as light, vibration or heat. Such IoT systems will also use non-volatile memory, either off- or on-chip, to store data when it is necessary to shut down. But for short period intermittent operation it can be better for performance and power saving not to shut down, which can cost thousands of machine cycles to bring the system up.

The technology also provides for dynamic switching, with a low power overhead, between active operation, in which the CPU core performs read and write operations of the embedded SRAM, and the standby mode, in which the stored data is retained, according to Renesas.

The SOTB process technology differs builds the active circuitry in a thin layer of silicon above the buried oxide. This allows the creation of dopant-less transistor channel structure, Renesas said. It also allows a reduction in transistor variation which, in turn, allows stable operation at voltages down to around 0.5V. The ability to control the silicon under the BOX layer allows provision of an on-chip regulator that can dynamically control the embedded SRAM substrate bias.

The embedded SRAM has three operating modes: normal, low-power and high-speed. By setting the substrate potential from zero bias to a forward bias, the read access time changes from 4.58ns to 1.84ns, which is 2.5 times faster compared to the normal mode, according to Renesas. By applying a reverse bias for standby mode the leakage current is reduced by three orders of magnitude to 13.7nW/Mbit, which is one-thousandth of the power consumption of the normal mode leakage power.

Renesas has also made a design approach to allow the fine-grained read-pulse optimisation, alleviating design margin considerations due to variability.