These days, there are strict regulations for saving energy that make "green" power conversion a major challenge. In particular, AC-DC conversion designed for telecom systems requires high efficiency over the entire load range of operation and across the universal mains input voltage range. Given the demand for more efficient, compact solutions, their design is becoming more challenging and new conversion approaches such as the digital, rather than the standard design based on analogue ICs, have been implemented. Specifically, while the standard approach is based on the use of a boost type PFC and a regulation stage, both controlled using analogue PWM controllers, the new, fully digital approach relies on the use of microcontrollers to control both the PFC and the DC-DC stages. This approach is increasingly being used for high density, high efficiency power electronics systems with high level flexibility of control. The growing complexity of the high power SMPS (switched-mode power supply), makes it difficult to design using only traditional analogue techniques. Using a digital approach in the power supply achieves higher efficiency, increasing the number of functionality and monitor features. There are several advantages of the digital control approach in the SMPS: 1) Programming flexibility: it is possible to update and improve the control logic, change the operating point on-the-fly, and to obtain control tuning more easily without hardware modifications; 2) Integration of communication functions and control algorithm in the same IC: continuous monitoring and reporting of the system status using standard protocols (PMBUS/SMBUS, CAN, PROFIBUS, Ethernet) and intelligent fault protections; 3) Possible use of GUI (Graphical User Interface); 4) Using advanced functionalities is possible: non-linear and multi-variables control techniques, programmable inrush control, and soft start function.

Overview of digital power supply
STEVAL-ISA172V2 is a 2kW AC-DC fully digital power supply board (figure 1).

EDNAOL 2016JUN01 TA 01Fig1 Figure 1: STEVAL-ISA172V2.

Figure 2 shows the block diagram of the solution. The system consists of two power stages controlled by two different STM32F334C8 microcontrollers: an input interleaved power factor corrector (PFC) and an output regulation stage implemented with a phase shifted full-bridge with zero-voltage-switching (ZVS) PWM and synchronous rectification (SR).

EDNAOL 2016JUN01 TA 01Fig2Figure 2: STEVAL-ISA172V2 block diagram.

The PFC is composed of two boost converters driven by two 180° phase shifted 60kHz PWMs generated by an advanced microcontroller peripheral, the high resolution timer (HRTIM), specifically designed to drive power conversion systems. The DC-DC stage performs voltage step-down from 400V to 48V using a Full Bridge and HF transformer with a primary to secondary turns ratio chosen to maintain good efficiency and regulation in the entire operating range. The transformer is supplied with a voltage with an average value dependent on the phase shift applied on the 100kHz PWMs of the primary side active switches. On the secondary side, this voltage waveform is rectified and then smoothed by the output filter. On the primary side, switching losses are reduced due to the ZVS (zero voltage switching), and a synchronous rectification on the secondary side is used to ensure low conduction losses. Communication between the primary and secondary parts is performed through bidirectional and opto-coupled serial communication.

Interleaved PFC
The PFC consists of a line bridge rectifier device and two boost converters. The two currents on the power devices are opportunely measured and sent to the ADC of the STM32F334C8 microcontroller. Another option is to apply the average control using the signal obtained from a shunt resistor. The choice of power semiconductors is fundamental to meet the efficiency requirements of the application. To meet the design requirements, two STW56N60M2-4 N-channel power MOSFETs have been selected for the PFC switches. This device, driven by a PM8834 gate driver, is characterized by a minimum breakdown voltage of 650 V and a maximum RDS(on) of 45 mΩ at 25°C for each switch. The total gate charge is 91 nC @ 52 A and VDD = 480 V. Thanks to the ST second generation of silicon carbide (SiC) diodes, STPSC1006, the behaviour of the boost diodes is very close to being ideal with negligible reverse recovery time, lower VF, and a high operating temperature (175°C). Using a 4-lead technology makes it possible to reduce switching losses, especially when the power level, and hence the current, are very high. In particular, the reduction of the on-switching loss is always present and increases with the power level, while the drop in the off-switching loss becomes more evident when the power level increases.

Control algorithm
The control algorithm of the interleaved PFC is implemented for the 32bit STM32F334C8 microcontroller from the STM32 family, which is provided with two independent high-speed 12bit ADCs, three ultra-fast comparators, and a high resolution timer (HRTIM). There are two different control loops: an outer voltage loop, performed at twice the mains frequency (100Hz or 120Hz), that provides the regulation of the bus voltage at the reference value (400 V), thereby setting the proper current reference, and an inner current loop, performed at up to 60kHz, that minimises the error between the average inductor current and its sinusoidal reference in phase with the mains voltage. The PLL is used to obtain the amplitude and phase of the mains voltage; the electrical angle is then used to reconstruct the sinusoidal input current reference (needed to obtain the DC voltage level at the desired value), in phase with the input voltage, thus maximising the Power Factor (PF) without depending on the input voltage distortions. The PFC section works properly not only in continuous conduction mode (CCM) but also when the converter operates in discontinuous conduction mode (DCM), due to light load or when the mains voltage is near the zero crossing, because of the feed-forward control technique. The feed-forward control technique is implemented to achieve a lower THD and to improve the transient response, reducing the output voltage overshoot caused by input voltage changes. The control algorithm is also able to shift the current reference in case it is necessary to compensate sampling delays and achieve a power factor close to unity. Experimental results
The efficiency of the system has been measured at different input voltages, in particular at 120V with 60Hz and 230V with 50Hz. The auxiliary power supply consumption is not included on PFC section because has been taken in to account on DC-DC efficiency measurements, as well the fan's consumption. PFC efficiency, Power factor, and waveforms are reported in figures 3, 4, and 5.

EDNAOL 2016JUN01 TA 01Fig3Figure 3: PFC efficiency at 120V and 230V.

EDNAOL 2016JUN01 TA 01Fig4Figure 4: Power Factor at 120 V and 230 V.

EDNAOL 2016JUN01 TA 01Fig5 Figure 5: Input current and voltage at 120 V AC 60Hz with 50% of the maximum load.

Full bridge phase shift ZVS DC-DC converter
The DC-DC converter adopted is a full bridge phase shifted step down converter, driven by a phase shifted modulation with a push-pull output stage. The purpose of the DC-DC stage is to step down the PFC output voltage from 400 V to 48 V and provide galvanic insulation using an HF transformer. This kind of modulation is used to achieve ZVS (zero voltage switching) and minimise turn-on switching losses, as opposed to classic PWM modulation in which hard switching and considerable power losses are present. For this reason, the full bridge phase shifted converter is suited for high power and high frequency applications. Each leg of the converter is implemented by a couple members of the new STW35N60DM2 high voltage N-channel 600V, 0.094Ω Power MOSFET MDmesh™ DM2 fast recovery diode series. It offers very low recovery charge (Qrr) and time (trr) combined with low RDS(on) and a low Coss, rendering it suitable for the most demanding high efficiency converters and ideal for bridge topologies and ZVS phase-shift converters. Each leg of the full bridge is driven with a couple of complementary 100kHz PWM signals from the high resolution timer with a fixed 50% duty cycle, using the PM8834 gate driver in combination with two pulse transformers. The modulation is implemented, using another STM32F334C8 microcontroller, by delaying in phase the two square waves of the lagging-leg with respect to the leading-leg, with a resolution of 217 ps from the HRTIM, obtaining a very precise output voltage regulation.

Synch rectification To improve the efficiency of the DC-DC, the synchronous rectification (SR) technique is necessary. It consists of replacing the output diodes with low voltage MOSFETs STW75NF20 low voltage N-channel 200 V, 0.028Ω typ., 75 A STripFET Power MOSFET TO-247 package, driven by the same STM32F334C8 microcontroller used for phase shift modulation and using another PM8834 gate driver. To avoid cross conduction in the SR MOSFETs, a delay time has to be considered between the beginning of diode conduction and the command given to the MOSFET gate. It is important to optimise the delay time of the MOSFET, which can be different for rising and falling edges of the two switches, in order to minimise diode conduction and improve efficiency.

Active clamp
Due to the energy stored in the transformer leakage inductance and the diode reverse recovery charge, there can be high voltage spikes on the synchronous rectification MOSFETs devices of the output stage. An RCD snubber circuit on this type of converter could be insufficient to properly clamp the over-voltage, and furthermore, an RCD circuit introduces additional thermal dissipations and decrement of the overall efficiency. Therefore, the STEVAL-ISA172V2 evaluation board includes two active clamp circuits, driven by the secondary side microcontroller (STM32F334C8), in order to reverse the extra energy directly to the output, and thus, prevent dissipative losses and hence obtaining higher efficiency.

EDNAOL 2016JUN01 TA 01Fig6Figure 6: Active clamp waveforms.

These over-voltages can be greater than the breakdown voltage of the devices, which therefore have to be protected. At the turn off of the device, the over-voltage is clamped by the charge on the clamp capacitor, and then this capacitor is discharged by an active resonant circuit that operates as a buck converter using two switches STP24N60DM2 N-channel 600 V, 0.175Ω, MDmesh DM2 Power MOSFET in TO-220 package, driven by a dual low side MOSFET PM8834 driver. Figure 6 shows the SR MOSFET voltage (yellow trace), the clamp capacitor voltage as spikes absorber (red trace), and voltage and current on the buck inductor (blue and green trace respectively). DC-DC efficiency
The DC-DC efficiency diagram is shown in figure 7. The obtained efficiency is more than 94% in the range of 650 W to 1300 W.

EDNAOL 2016JUN01 TA 01Fig7Figure 7: DC-DC efficiency versus the output power.

Experimental results The overall efficiency of the STEVAL-ISA172V2 (figure 7) has been considered at different loads using an electronic load set in continuous current. The input and output voltage and current were measured directly on the input output board connectors. The total efficiency of the overall system is shown in figure 8 and can be considered near 92% around 1000W of output power at 230V input AC voltage.

EDNAOL 2016JUN01 TA 01Fig8 Figure 8: Total efficiency of the overall system.

This article describes the 2kW digital power supply developed by STMicroelectronics and how the digital control, based on 32bit MCUs from the ST32 family, plays a key role in the flexibility of the control strategy, allowing control techniques such as the feed-forward algorithm and further improvements of control logic as well as an easier control tuning without hardware modifications. An active clamp on the output stage is also implemented with a dedicated microcontroller routine. The experimental results show power factor near unity and low THD% under wide input voltage and load conditions due to the performance of the power products as well as the control strategies implemented on the 32bit F334 microcontrollers.

About the authors
Ivan Clemente Roberto Massimiani received the bachelor's degree in Electronic Engineering and master's degree in Automation Engineering and Control of Complex Systems from the University of Catania, in 2008 and 2011, respectively. Since 2011 he has been a system Engineer at STMicroelectronics in Catania, Italy, in the field of Power Electronics. He has been involved in the design of inverters for Motor Control and power conversion systems for industrial and automotive applications. Today he is in charge of the development and implementation of control techniques in microcontroller based SMPS. Mario Di Guardo received the Master's degree in Electrical Engineer from the University of Catania Italy. He joined STMicroelectronics in 1996 as a system engineer in the field of electronic control. Since 1997 he has focused on inverters and drives for motor control. STMicroelectronics Technical Staff Member SMPS & high power systems since 2011. Today he is involved in definition of power conversion systems as digital SMPS and reference design for customers. He is the author of several technical articles and patents.