Intel has pledged to support the former Altera’s base business, including use of ARM cores and long product lead times at the first event of the merged x86 and FPGA makers. In a Q&A session, CEO Brian Krzanich also provided some insights on the company’s acceleration strategy in light of its recent acquisition of start-up Nervana.

“More than 50% of value if the [$16 billion Altera] acquisition was actually tied to growing Altera at a faster rate than it was growing,” said Krzanich in the first ISDF event.

As an example, Krzanich pledged to ship before the end of the year Altera’s flagship, the Stratix 10 FPGAs. It will wear the Intel brand and use both Intel’s 14nm process technology and be the first chip to use its embedded multi-die interconnect packaging technology.

EDNA Intel 01 Figure 1: Krzanich showed a Stratix 10 FPGA that will ship this year under the Intel brand. (Images: EE Times)

Kraznich promised “no changes in existing or planned products” using ARM cores.

“There is no plan to yank ARM out [of FPGAs] and stick in [Intel architecture (IA)] and make you all change your programming models,” he told an audience of several hundred FPGA developers. “There are some advanced products that may like an IA core but my guess is the majority of them won’t—that would be wasted money on our part and trouble for our customers,” he said.

“The default processor [to embed in FPGAs] will be ARM—I want to make sure we kill any of that question or debate,” Krzainch said. “There will be some level of performance at the high end with Xeon and FPGAs—we’re shipping a co-packaged product today and we will talk about generating many more of these—and we think there will be a class of performance at the upper end of the data centre that will need these capabilities."

In response to a question, Krzanich reaffirmed Intel is working on products that will combine Xeon server processors, FPGAs and 3D XPoint memories on Intel Omnipath fabrics. However he declined to give any details on such chips or when they will ship.

A year ago when the Altera deal was announced, “customers had a wait-and-see attitude and a concern we would be a data centre play,” said Dan McNamara, a former Altera executive who now manages Intel’s FPGA division. Today “customers see the investments, road maps and improvements, and I feel we’ve mitigated a lot of the concern,” he said.

On stage for a Q&A session, McNamara teased Krzanich about Intel shirts given to attendees. “Have you ever dressed a room full of ARM developers like this before?” he asked.

“No, this is a first but I promise it won’t be the last,” Krzanch shot back to applause.

Intel evaluating Nervana’s machine-learning ASIC

The Intel CEO said he is leaving the Altera sales and support teams in place while encouraging interaction between engineers. “You should see nothing but an improvement in service and support in the next few years,” Krzanich said.

In addition, he said Intel will commit to product life cycles “well beyond 15 years if that’s what’s required,” he said. “The average life time of a silicon technology at Intel is 12 years—we still manufacture products at 65nm even though we are starting to sample wafers internally at 10nm,” he added, giving a rare indication of the status of Intel’s next-generation process.

He also reinforced support for Altera’s low-end products, noting Intel already supports microcontroller-class processors with its Quark as part of its drive into the Internet of Things. “We will have [processors] well below those [Quark chips] coming later,” he hinted.

Altera is a key part in Intel’s overall strategy because FPGAs and memory are two central parts of computing where the company aims to differentiate itself, Krzanich said in a nod to its upcoming 3D XPoint memories.

One engineer in the audience said he hopes the acquisition results in improved FPGA tools, noting the Altera Quartus designers might benefit from Intel’s compiler expertise. Routing the largest FPGAs is still too slow, the engineer said, noting Quartus updates in the past year showed only incremental improvements.

EDNA Intel 02 Figure 2: Dan McNamara (left) said his Intel FPGA division has started an engagement about tools with Intel's system software group.

McNamara said his division is “working hard on foundation flows…and is kicking off a new engagement with [Intel’s] systems software group” to work on “an over-arching model.”

Asked about Intel’s strategy for accelerators given its existing multicore Xeon Phi, new FPGAs and recent acquisition of Nervana, Krzanich said the chips have unique attributes that attract different workloads.

Nervana’s machine-learning ASIC “just came out and we are still evaluating whether that ASIC and its algorithms will become part of Xeon [or a] stand-alone [chip] or it goes away… the real value is more [the start-up’s] machine learning algorithms and tools,” Krzanich said.

FPGAs shine as accelerators because they can “in a millisecond switch to do another algorithm, so they are very flexible to react to changing workloads,” said McNamara.

Asked if Intel’s foundry business will make Altera FPGA fabrics available, Krzanich showed the same agnostic approach he expressed about ARM cores. “We haven’t had anybody ask but I don’t see why not…[as long as Intel is] not giving up our IP,” he said.