SoC interconnect IP supplier Arteris has rolled out the Piano 2.0 timing closure package, which builds on customer silicon experience gathered with FlexNoC Physical package to automate interconnect timing closure for both cache coherent and non-coherent subsystems.

On-chip interconnect has become a prime source of timing closure issues due to the increased use of smaller geometry semiconductor processes and FinFET transistors. These issues are usually found late in the design process which causes schedule slips and delayed time-to-market. Design teams currently deal with these issues by manually inserting pipeline stages in the chip netlist through an engineering change order (ECO) process.

To address these issues, the Piano 2.0 solves back-end timing problems with technology that works earlier in the SoC design flow, thus reducing schedule risk. Arteris said its new technology introduces the concept of physical interconnect distance to customers using Arteris FlexNoC and Ncore interconnect products.

First, Piano calculates the length of individual interconnect links and traces, and then uses information about the semiconductor technology process and performance targets to automatically add interconnect pipelines to close timing. Then Piano helps validate this timing closure scheme with the physical synthesis capabilities of the Synopsys or Cadence tool chains.

The Piano 2.0 slashes the time needed to close timing compared to manual pipeline insertion methodologies, which reduces overall schedule risk. With a well-defined methodology, interconnect timing can be closed in as little as 24 hours.

The interconnect timing platform shrinks interconnect area by 10-15% compared to manual pipeline insertion methodologies, while also decreasing interconnect power consumption due to less pipeline logic and use of fewer low voltage threshold (LVT) cells. In addition, Piano 2.0 provides seeding of pipeline stage locations which allows place and route tools a better starting point.

Arteris said Piano 2.0 is capable of automated interconnect timing closure for both cache coherent and non-coherent interconnect subsystems; generation of a meta-floorplan from an IP list to provide timing closure guidance during the SoC architectural development phase; input and output of production floorplans in LEF/DEF and TCL formats; and automatic pipeline insertion. It is also integrated with Synopsys’ Design Compiler Graphical and IC Compiler II and Cadence’s Genus and Innovus physical synthesis tool chains.

The PIANO 2.0 Timing Closure Package is available immediately as an add-on for FlexNoC and Ncore interconnect IP licensees, with additional features being available in the second quarter of 2017.