While working on a motorised hospital bed project, Slava Zilberfayn finds out a lot could go wrong when resistor drivers are used for power FETs.
I was recently involved in designing the electronics for a motorised hospital bed. It was a simple device to make; we only needed to enable a few keypads and six actuators in both directions.
The competition uses a pair of relays to switch the direction of the motor, but we decided to use FETs arranged in an H-bridge. A classic circuit, and not our first circuit for motor controls, either. What could possibly go wrong? Turns out, a lot.
After initial prototype was assembled, testing began. Everything seemed to work fine, but for some reason when I switched direction quickly (i.e., pressing up and down buttons in a quick succession), the lab power supply would sometimes momentarily blink a red LED indicating that current limit had been tripped. But why? The board is being tested by itself, no loads attached (just tiny LEDs). The only explanation for that is that somehow the bridge is short circuited.
The software that controlled the drivers was re-examined, the signals controlling the FET drivers were validated with an oscilloscope, and it was confirmed that we definitely turned everything off before turning on the bridge in the opposite direction. But the problem persisted.
However, if I introduced at least a 10ms delay during switching the direction the problem goes away. I guess that's a solution, right? For all practical purposes this delay does not make any difference as it can't possibly be observed by a user. But I was really not comfortable with putting a device that exhibits an unexplained behaviour into production. I had to get to the bottom of it.
Let's take a look at the schematics. The customer wanted to keep the cost down, so we did not use any dedicated FET-driver ICs. As you can see below, the top gates (Q1) are controlled by a really primitive voltage divider and the bottom gates (Q2) have a more elaborate driver. In practical terms, the bottom driver has a switching speed of about 1µs and the top driver is around 100µs. The compromise was well understood. We weren't sure if we were going to need PWM capability (for example, to do soft start/stop) on all six channels, but if we did, the idea was that we could keep one of the top gates turned on and PWM the bottom gate. So, slow top drivers were sufficient for the application.
The change direction routine naturally was aware of slow top drivers, there was a delay of 200µs between turning on the left gate and turning on the right one (and vice versa).
Spacing apart each gate switching event quickly revealed that the problem coincides with turning on the bottom gate. At that moment, all hell breaks loose. The 12V line collapses, the 24V line collapses (it is current limited by the power supply), and output of the bottom driver oscillates for 10-15µs before finally everything settles down. What is going on?!
At the same time the ground return path of the bridge showed significant surge. Initially I thought that this ground bounce is large enough to close Q39, which in turn would open up the wrong side of the bottom of the bridge. Quite possibly that was true too, as directly connecting the CPU ground and bridge ground stopped overcurrent tripping. But where was the original ground bounce coming from anyway? The layout of the ground was re-examined again, and again, and nothing was wrong with it. Connecting grounds did not make any sense and so it could not be a solution.
By then the problem was sufficiently analysed to point me in the direction of the top driver. Indeed, reducing resistors R1 and R15 to 500Ω lowered the amount of ground bounce and stopped the overcurrent tripping. But the problem was still there, just significantly reduced.
And then I realized what was going on. After I turn on, for example, the left top gate (Q1B), both of bridge's outputs are at 24V (because they are connected through the load and the bottom gates are off). When I turn on the right bottom gate (Q2A), I have a capacitive voltage divider (Cgd & Cgs) formed by the top FET Q1A, with the gate being the middle point of the divider. The rush of current to charge the capacitors puts the top gate at −12V relative to the source, and this turns on the top right gate. Now the current flows straight through the right side of the bridge, and I observe the ground bounce, which also turns on the left bottom gate. Now all four gates are open! The 24V line starts collapsing and this in turn brings the 12V line down as well.
In hindsight, it seems almost obvious. I mean, why do we need fast and powerful FET drivers if we don't intend to do fast switching? Oh well, lesson learned; no more resistor drivers for power FETs!
Slava Zilberfayn runs a small electronics consulting business that focuses on development of various hospital equipment.