Here's a 31st-order, parallel-PRBS generator that delivers 10bit output segments and can easily adapt to other PRBS orders and output widths.

Pseudorandom-binary-sequence (PRBS), or pseudonoise (PN), generators find a broad range of applications in digital-data transmission (**Reference 1**). These circuits often comprise simple shift registers with feedback that can serve as test sources for serial-data links. As their name implies, the output sequence is not truly random and in fact repeats after 2^{N}–1 bits, where N denotes the shift register's length. Polynomial notation, in which the polynomial order corresponds to the shift register's length and, thus, the PRBS' period provides a convenient method of describing the sequence.
Communications-equipment tests use certain standard polynomials. For example, x^{7}+x^{6}+1 yields a PRBS period of 127 bits, x^{23}+x^{18}+1 yields a period of more than 8 million bits, and x^{31}+x^{28}+1 yields a period that's 256 times longer. A PRBS with a longer period generally produces a greater variety of data patterns that more thoroughly check the transmission system's performance.
A simple shift register with feedback from an intermediate stage can generate a PRBS. The flip-flops constituting the register must run at a speed equal to the transmission speed, which may pose a problem if you want to build a long-period PRBS generator that runs at a gigahertz clock rate. A high-speed serialiser such as Texas Instruments' TLK2201B, which runs at data rates as high as 1.6Gbit/s, offers one potential solution to the problem. However, instead of accepting a PRBS in its natural fully serial format, the serialiser accepts only 10bit portions at a time.

**Figure 1:** This circuit implements a 10bit parallel-output PRBS generator defined by the polynomial equation x311x2811. To reduce clutter, the schematic shows only one of 10 exclusive-OR gates that generates the register's feedback signals. A common clock source (not shown) drives all 31 flip-flops' clock inputs.

The circuit in **figure 1** illustrates a 31st-order, parallel-PRBS generator that delivers 10bit output segments and can easily adapt to other PRBS orders and output widths. To design the circuit, begin by drawing a diagram with 31 flip-flops arranged in rows containing nominally 10 flip-flops. In this instance, the design comprises four rows, with only one flip-flop in Row 1. **Figure 1** shows the timing relationships among the flip-flops and the numbering convention.
The resulting structure forms a parallel shift register, with the fourth row fed directly from the third row, the third fed from the second, and so on. Flip-flops 10 through 2 in Row 2 and flip-flop 1 in Row 1 receive their inputs from the feedback path. This arrangement ensures that flip-flops in consecutive rows always deliver their outputs 10 time instants apart, and the generator's clock thus runs at one-tenth the speed of an equivalent serial-shift-register PRBS implementation.
To determine the feedback signals, derive the equation that describes a standard—that is, serial—PRBS generator's output, which, for a polynomial of x^{31}+x^{28}+1, yields: y(n)=y(n–31) xor y(n–28). Using that equation, you can derive the equations that describe feedback signals fdbk1 through fdbk10. That is, fdbk1: y (n+9)=y(n–22) xor y(n–19), fdbk2: y(n+8)=y(n–23) xor y(n–20), ... fdbk10: y(n)=y(n–31) xor y(n–28). For example, feedback signal fdbk1 derives from the output of a two-input exclusive-OR gate driven by the outputs of flip-flops 22 and 19.

* **Figure 2:** A pseudorandom sequence produces this eye diagram as measured at the output of a TLK2201B serialiser that an FPGA-sequence generator drives.*

**Listing 1** contains the VHDL code that implements the circuit of **figure 1** in either a CPLD or an FPGA device. Lines 15 through 18 define the parallel-shift register, and lines 21 through 23 define the feedback circuit's construction. The circuit in this Design Idea fits into an XC3S50 Spartan 3 device from Xilinx, runs at a 150MHz clock rate, and drives a Texas Instruments TLK2201B serialiser at 150MHz through a 10bit interface. Xilinx's ISE 7.1i software compiled the circuit's VHDL files. **Figure 2** displays an eye diagram for the serialiser's output and confirms the circuit's operation at 1.5Gbit/s. The compilation software predicts that the circuit should run at clock rates exceeding 300MHz, but the TLK2201B limits operation to 150MHz.
**Reference**

Miller, Andy, and Mike Gulotta, "PN generators using the SRL macro," Application Note APP211, Xilinx Inc, June 15, 2004.
*This article is a Design Idea selected for re-publication by the editors. It was first published on March 29, 2007 in EDN.com.*