Knowing how to predict reference spur level helps pick loop parameters wisely during the early stages of a PLL system design.
The phase locked loop (PLL) is a negative feedback system that locks the phase and frequency of a higher frequency device (usually a voltage controlled oscillator, VCO) whose phase and frequency are not very stable over temperature and time to a more stable and lower frequency device (usually a temperature compensated or oven controlled crystal oscillator, TCXO or OCXO). As a black box, the PLL can be viewed as a frequency multiplier.
Linear Technology has provided a simple model that can be used to accurately predict the level of reference spurs due to charge pump and/or op amp leakage current in a PLL system. Knowing how to predict these levels helps pick loop parameters wisely during the early stages of a PLL system design.
A PLL is employed when there is the need for a high frequency local oscillator (LO) source. Example applications are numerous and include wireless communications, medical devices and instrumentation.
The PLL integrated circuit (IC) usually contains all clock dividers (R and N), phase/frequency detector (PFD) and the charge pump, represented by the two current sources, ICP_UP and ICP_DN.
Integer-N PLL operation and nonidealities are important topics in the design of RF systems. Reference spurs can have a significantly negative impact on overall system performance. The simple model provided by Linear Technology accurately predicts reference spur levels due to leakage current in PLLs and can be a useful design tool, significantly reducing the number of board revisions required to reach a desired solution.
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