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Read and write commands are driven by the control inputs (LDA#, RWA#, LDB# and RWB#) and the address inputs. Port A control inputs are sampled at the rising edge of the input clock (CK). Port B control inputs are sampled at the falling edge of the input clock. Table 1 shows the conditions for Port A and Port B read/write operations.

QDR-IV_01 (cr) Table 1: Port A and Port B read/write condition are shown.

As figures 1 and 2 show, Port A read data comes out of the DQA pins exactly five read latency (RL) clock cycles after the rising edge of CK for QDR-IV HP SRAM and eight RL clock cycles after the rising edge of CK for QDR-IV XP SRAM. The data is available after the number of RL clock cycles from the rising edge of the CK signal when the READ command was issued.

QDR-IV_02 (cr) Figure 1: This figure shows the read timing.

The Port A write data is supplied to the DQA pins exactly three write latency (WL) clock cycles after the rising edge of CK for QDR-IV HP SRAM and five WL clock cycles after the rising edge of CK for QDR-IV XP SRAM. The data comes after the number of WL clock cycles from the rising edge of the CK signal when the WRITE command was issued.

QDR-IV_03 (cr) Figure 2: This figure shows the write timing.

The Port B read data comes out of the DQB pins exactly five RL clock cycles after the falling edge of CK for QDR-IV HP SRAM and eight RL clock cycles after the falling edge of CK for QDR-IV XP SRAM. The data is available after the number of RL clock cycles from the falling edge of the CK signal when the READ command was issued.

The Port B write data is supplied to DQB pins exactly three WL clock cycles after the falling edge of CK for QDR-IV HP SRAM and five WL clock cycles after the falling edge of CK for QDR-IV XP SRAM. The data comes after the number of WL clock cycles from the falling edge of the CK signal when the WRITE command was issued.

The QVLDA/QVLDB signals indicate valid output data at the respective port. QVLDA and QVLDB are asserted a half-clock cycle before the first data word driven on the bus and de-asserted a half-clock cycle before the last data word driven on the bus. Data outputs are tri-stated following the last data word.

Banking scheme for high-speed operation

The QDR-IV XP SRAM is divided into eight banks to operate at higher frequencies for a maximum operation frequency = 1,066MHz. QDR-IV HP SRAM operates in non-banked mode at lower frequencies for a maximum operating frequency = 667MHz.

The lower three address pins (A2, A1 and A0) in QDR-IV XP select the bank that will be accessed during the read or write operation. The only banking restriction is that a particular bank can be accessed only once each clock cycle. The bank access rule for QDR-IV XP SRAM necessitates that the bank address accessed on Port B cannot to be same as bank address accessed on Port A.

If a banking violation occurs, the read/write operation on Port A is unrestricted as it is sampled on the rising edge of the clock while that on Port B is denied. The QDR-IV HP SRAM does not have any banking restriction.

QDR-IV_04 (cr) Figure 3: *Here is the write/read operation for QDR-IV XP SRAM. *

QDR-IV_05 (cr) Figure 4: Here is the write/read operation for QDR-IV HP SRAM.

The banking restriction on QDR-IV XP SRAM may be looked upon as an advantage in applications where each bank of memory is used for different purposes and is not being accessed in the same clock cycle twice. One example could be where a network router can store different routing tables in each bank of the QDR-IV XP SRAM. If a particular routing table is not accessed more than once during the same clock cycle, it is possible to achieve high RTRs. In such applications, the maximum RTR that can be achieved is 2132MT/s with an operating frequency of 1,066MHz.

Another scenario where the banking restriction does not hinder the transaction rate is in designs with multiple ports at the physical layer with each port directed toward one of the banks in memory. These ports would be multiplexed to Port A and Port B of the QDR-IV XP SRAM. In this configuration, no single bank can be accessed in the same cycle twice as each bank is connected to different ports at the physical layer.

However, one can access the same bank again in one clock cycle period if the first access to the bank is through Port B on the falling edge of the current clock cycle and the second access is through Port A on the rising edge of the next clock cycle. In Figure 5, during the write sequence, both Port B and Port A access bank Y in one clock cycle period. Similarly, Port B and Port A access bank X during the read sequence in one clock cycle period.

QDR-IV_06 (cr) Figure 5: This figure shows access to the same memory bank in one clock cycle period.

Pritesh Mandaliya is a staff applications engineer in the Memory Product Division of Cypress Semiconductor. He holds a master’s degree in electrical engineering from San Jose State University.

Anuj Chakrapani is a senior applications engineer at the Memory and Imaging Division of Cypress Semiconductor. His responsibilities include creating behavioral simulation models of SRAMs, board-level failure-analysis debug, system-level testing, and applications support for customers. Anuj holds a master's degree in electrical engineering from Arizona State University (Tempe).

First published by EDN.

 
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