Synopsys's latest DesignWare ARC SEM110 and SEM120D security processors offer advanced security features such as uniform instruction timing and power randomisation for low-power, embedded applications such as smart metering, NFC payment and embedded SIMs.

The DesignWare ARC SEM processors are based on the scalable, 32-bit ARCv2 instruction set architecture (ISA) and are optimised for area and power efficiency. The ARC SEM110 processor integrates a wide range of security technologies and can be implemented in an SoC as either a standalone secure core or as a single core performing both secure and non-secure functions. The ARC SEM120D adds DSP functionality for applications such as sensor processing and voice identification in health care and IoT devices. Key features of the new processors include:

The new ARC SEM processors with Synopsys SecureShield technology enable designers to protect systems against software, hardware and side-channel attacks as well as separate secure and non-secure functions as part of a Trusted Execution Environment (TEE). In addition, the SecureShield Runtime Library manages the partitioning and isolation of containers within a TEE to ensure data is stored and processed in a safe environment. This combination of hardware and software features enables designers to create more secure system-on-chips (SoCs) for IoT and mobile applications.

EDNA ARC Figure 1: ARC SEM security processor block diagram (Source: Synopsys)

The ARC SEM processors with SecureShield are part of Synopsys' comprehensive portfolio of security IP solutions that include the Enhanced Security Package and CryptoPack options for ARC EM processors and the DesignWare Security IP solutions, which consist of a range of cryptography cores and software library, protocol accelerators, root of trust, platform security and content protection IP.

The DesignWare ARC SEM110 and SEM120D processors are scheduled for general availability in October 2016.