« Previously: QDR-IV supports deskew training sequences  
System designers must rely on techniques such as off-chip error correction or redundancy to achieve higher reliability. These techniques result in overhead, in terms of either PCB space or additional processing time. QDR-IV offers a single-chip implementation with on-chip error correcting code (ECC), thus reducing board space, cost and design complexity. It also reduces the overall soft error rate (SER) of the QDR-IV memory array. This feature covers both x18 and x36 data bus-width options and will always be enabled in the SRAM. The ECC protection provides single-bit error correction (SEC).

QDR-IV generates the ECC parity bits internally from the input data and stores them in the memory array. The memory array contains extra bits, which are required to store the ECC parity. However, these extra internal parity bits are not brought out to the external pins.

For example, Figure 1 shows the output data logic diagram for a x36 device. There are six ECC parity bits for 36 data bits; therefore, 42 bits (36 data bits + 6 ECC parity bits) arrive to the ECC logic from memory core. As a result, ECC logic provides 36 bits of corrected output data.

QDR/DDR SRAMs without ECC typically have an SER failure in time (FIT) rate of 200 FIT/Mb. This number improves to 0.01 FIT/Mb with ECC, which provides an improvement of four orders of magnitude.

QDR-IV design 01 (cr) Figure 1: The output data logic for a x36 option

Design recommendations for QDR-IV memory controller

This section provides some memory controller design recommendations, when address parity and bus inversion features of the QDR-IV are enabled. The memory controller must generate address parity based on the address bus first. Address inversion should be done at a later time on the address bus and address parity bit.

For data bus inversion, the memory controller needs to count the number of logic 0s in the respective DQ bus to generate the corresponding DINV bit (based on the data bus inversion condition) before sending the data to QDR-IV.

QDR-IV uses the same logic for data bus inversion while transmitting data to the memory controller. To identify the received data from QDR-IV, the controller only needs to check the status of the corresponding DINV bit. If the controller receives DINV = 1, then it needs to invert the relevant data bus; otherwise the received data bits must remain unchanged. Figure 2 shows the design consideration for the memory controller.

QDR-IV design 02 (cr) Figure 2: Design consideration for memory controller


QDR-IV, with a maximum RTR of 2132 MT/s, is the highest performance, standards-based memory solution available in the market. Its high RTR, coupled with differentiated features such as dual bidirectional ports, ECC, bus inversion, ODT and address parity, make it an excellent solution for networking systems. The advantages of QDR-IV also apply to other systems that require high-RTR performance and signal integrity, such as high-performance computing and image processing.

Pritesh Mandaliya is a staff applications engineer in the Memory Product Division of Cypress Semiconductor. He holds a master’s degree in electrical engineering from San Jose State University. Anuj Chakrapani is a senior applications engineer at the Memory and Imaging Division of Cypress Semiconductor. His responsibilities include creating behavioral simulation models of SRAMs, board-level failure-analysis debug, system-level testing, and applications support for customers. Anuj holds a master's degree in electrical engineering from Arizona State University (Tempe).

First published by EDN.  
« Previously: QDR-IV supports deskew training sequences