PLDA has launched its XpressRICH4-AXI PCIe 4.0 IP for integrating AXI and PCIe blocks.

Project teams on multicore SoC design strive to preserve PCIe performance and prevent integrity errors while adding AXI capabilities. Integrating AXI into PCIe applications involves adding an AXI block, but does not provide a true bridge. This requires the SoC designer to manually adjust errors and attempt to optimise PCIe and AXI performance unaided.

PLDA’s XpressRICH4-AXI provides seamless integration between the PCIe Interface and the AXI bus, enabling seamless interconnect, preventing AXI deadlock and delivering full PCIe performance on the AXI side, while reducing the risk of errors in the AXI block.

 
PLDA XpressRICH4-ASIC fig1 (cr) Figure 1: XpressRICH4-AXI PCIe 4.0 interface for ARM embedded processors, boasts architecture and features specifically engineered for AMBA AXI-based SoC.  

XpressRICH4-AXI features a fourth generation PCIe controller to guarantee reliability, robustness, and initial silicon success. The integrated AXI bridge provides advanced features that extend AXI functionality, including: • Native PCIe features like AER (Advanced Error Reporting) which enables application-specific error management thereby simplifying application software. • Ordering rules observance, including the ability to split into different size packets and merge between AXI and PCIe. This feature prevents hazards and deadlocks while ensuring optimised traffic flow. • Multiple flexible options to configure the AMBA AXI Interface, including multiple combinations of AXI Master, AXI Slave and AXI Stream interfaces with different data paths, such as 64-bits, 128-bits and 256-bits • A built-in AXI interconnect with up to 4x Master/Slave, 4x Stream and Lite (Master/Slave) interfaces that can be combined together

The PCIe-AXI integration paves way for time-to-market and cost-to-market advantages for PCIe 4.0 and AXI bus users.