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eInfochips Announces DDR2 SDRAM Verification IP and Reed Solomon Encoder Design IP

EInfochips has announced the availability of JEDEC (JESD79-2D) compliant DDR2 SDRAM (Double-Data-Rate-Two Synchronous Dynamic Random Access Memory) verification IP and European DVB, IEEE 802.16, IntelSat Earth Station (IESS), ETS 300 421 and ETS 300 429 standards compliant Reed Solomon encoder design IP. eInfochips’ DDR2 SDRAM verification IP (VIP) can be used to verify JEDEC standard (JESD79-2D) based DDR2 SDRAM memory model(s). The Reed Solomon design IP is designed for efficient implementation on FPGA and ASIC and can be used for communication ...

 
 
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November 2008
COVER STORY:

Electronic-system-level design: Is there fire beneath the smoke?

It was a shimmering promise on the horizon: As SOCs (systems on chips) became more complex, we would simply move from RTL (register-transfer level) to the next-higher level of abstraction—what some experts called ESL (electronic-system-level) design. We would express the behavior of the system in a ...
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