CNN accuracy with flexible milliwatt FPGA solutions; New reference designs for human presence and hand gesture recognition with scalable performance/power
PORTLAND, OR – September 25, 2018 – Lattice Semiconductor Corporation (NASDAQ: LSCC) today unveiled expanded features of the company’s popular Lattice sensAI™ stack designed to speed time-to-market for developers of flexible machine learning inferencing in consumer and industrial IoT applications. Building on the ultra-low power (1 mW-1 W) focus of the sensAI stack, Lattice is releasing new IP cores, reference designs, demos and hardware development kits that provide scalable performance and power for always-on, on-device artificial intelligence (AI) applications.
“Flexible, low-power, always-on, on-device AI is increasingly a requirement in edge devices that are battery operated or have thermal constraints. The new features of the sensAI stack are optimized to address this challenge, delivering improved accuracy, scalable performance, and ease-of-use, while still consuming only a few milliwatts of power,” said Deepak Boppana, Senior Director, Product and Segment Marketing, Lattice Semiconductor. “With these enhancements, sensAI solutions can now support a variety of low-power, flexible system architectures for always-on, on-device AI.”
Examples of the architectural choices that sensAI solutions enable include:
Updates to the sensAI stack include:
The Lattice sensAI partner eco-system continues to expand worldwide with new design service and IP partners focused on enabling smart home, smart factory, smart city, and smart car applications. “Lattice’s low power, small size FPGAs and neural network IP cores and tools, will significantly accelerate adoption of artificial intelligence at the edge,” said Amit Vashi, Chief Operating Officer, Softnautics, a sensAI Design Services partner. “With our expertise in machine learning, we are proud to be working closely with Lattice to enable sensAI solution deployments as evident by our jointly developed vehicle classification demo using ECP5 FPGAs”.