Take an in-depth look at full-chip ESD protection verification, and how new automated verification tools and methodologies are helping to deliver more reliable products.
Designing an integrated circuit (IC) for communication, computing, gaming, and other emerging applications is a multi-million dollar project, requiring rigorous design methodology and substantial cross-team collaboration. Successfully fabricating these devices using advanced sub-micron process nodes requires the use of state-of-the-art verification processes at every critical point in the design flow.
Building verification steps into the design process helps ensure the chip will function as designed, that it complies with all design rule checks (DRC) and timing constraints, and that it conforms to the targeted chip area size. For mobile applications, designers must pay even greater attention to power analysis and management than usual. And, where advanced process nodes are being used, design for manufacturing (DFM) rules are often applied to increase silicon yield.
But what about reliability? ICs face a myriad of issues that could limit their performance, service life, or both. This includes electrostatic discharge (ESD), latch-up, electrical overstress (EOS), and time-dependent dielectric breakdown (TDDB), all of which must be evaluated during the verification process. Traditionally, these concerns are addressed in devices and gate cells during library development at each technology node. This, however, may be insufficient for extremely complex devices, ICs designed to operate under multiple power domains, and/or ICs being manufactured at an advanced process node. In these cases, reliability issues can re-emerge in the device’s interconnect network, or elsewhere.
With all these factors in play, it has been challenging to verify reliability/ESD protection at a full-chip level. Recently, this has begun to change with the growing availability of automated reliability verification tools and methodologies. In this article, we’ll take an in-depth look at full-chip ESD protection verification, and how new automated verification tools and methodologies are helping to deliver more reliable products to the market.
Full-chip ESD verification
ESD was one of the first reliability issues to be identified in the early days of IC design. Since then, continuous research on ESD device dynamic behavior has resulted in the development of robust, well-characterized ESD protection devices for each new process technology node. While these ESD protection devices/cells are available for use in chip layout implementation, verifying that a chip with complex arrays of I/O, power, and ground ports is protected from the wide variety of potential ESD events is still a daunting task in most advanced node chip design projects. Failure to detect an ESD vulnerability in a layout can result in delay of product launch and/or significant financial loss, particularly if the vulnerable product reaches the market.
These issues typically reveal themselves when designers perform full-chip level ESD verification at the chip assembly stage for tape-out. The traditional way to verify a design is protected from ESD events is by manual inspection of the layout, using a list of guidelines. However, only a few top-tier foundries provide ESD design guidelines in their design rules manual (DRM). Although some of these guidelines are implemented in DRC, with the assist of a marker layer to detect the needed checking area, the remainder are simply textual descriptions.
Because of this limitation, and because the last stage of tape-out typically demands quick turnaround, this manual verification usually requires the time-consuming involvement of ESD engineers. In fact, in established design houses, ESD design know-how is often considered a design secret and a competitive advantage. Coverage of foundry DRC rules for ESD verification is, however, very limited; using manual inspection to perform the remainder of ESD rules verification can no longer be justified as part of an efficient production design tape-out flow.
In an effort to handle the growing complexity of ESD verification more efficiently, some companies have developed their own in-house utilities, but they still struggle to keep up with changing technology and layout designers’ requirements. For emerging applications, ESD experts often lack the familiarity and experience with their specialized needs. For these, and other reasons, manual ESD checking methodology has simply become unsustainable in a rigorous design environment.
Foundries need automated ESD verification methodologies that allow them to convert their ESD guidelines into qualified full-chip ESD design verification kits, thereby providing enhanced service to their customers. Design houses also benefit from automated ESD tools and methodologies, which eliminate time-consuming manual verification and ensure fast, accurate full-chip ESD protection verification, even for complex advanced node designs.
Automated ESD verification
Logic-driven layout checks
Chip-level ESD protection verification must consider circuit connectivity in conjunction with correlated layout geometric and electrical data. The dynamic simulation methods traditionally used to analyze ESD protection are not feasible at the full-chip level, and are rarely successful in a working production design tape-out flow. Instead, a rules-based (static) approach can be implemented using specialized EDA tools to perform full-chip context-aware ESD verification that checks not only for the existence of ESD protection circuits, but also the robustness of the interconnects used within these circuits to transport and dissipate the energy of an ESD event.
Automated ESD design verification must operate on a layout database (GDS or OASIS) as part of the design tape-out process. ESD protection circuits and ESD current paths are integral parts of the designed circuitry on I/O, power, ground, and cross-power-domain nets/paths. Designers must be able to select ESD protection circuits and their corresponding physical layout data, and assign ESD current path staging through ports/pads and device pins for ESD-related geometrical and electrical properties checking. The two primary verification processes include:
Implementing these processes as automated rule checks requires an EDA tool capable of traversing the design logic (topology) while accessing the device’s physical layout properties and its corresponding requirements (layout geometrical/electrical property scheme), as defined by rule checks. Specialized reliability verification tools are available that use a logic-driven layout check methodology to provide designers with an automated process that performs accurate, context-aware ESD verification. These tools also enable rule deck writers to effectively manage the complexity of ESD check processes and to present the results in an intuitive format that makes it easier for designers to debug errors and identify new opportunities for improvement.
Let’s look at some general practices for verifying chip-level ESD protection using an LVS extracted layout netlist from a (typically) GDSII/OASIS layout database for design topology traversal.
ESD protection circuits between I/O and internal gates
One required step for ESD verification at both the block and chip level of a design is to check to see if each of the appropriate ESD/power clamping protection circuits are connected:
These protection circuits consist of different devices, such as pull-up/pull-down diodes, NMOS, PMOS, ESD resistors, and back-to-back (B2B) diodes, as shown in Figure 1. The protection circuit can be connected in a cascaded structure, or tied to RC circuits. Their components’ values, and interconnect structure will vary according to what that types of ESD hazards they will be protecting against, and the voltages applied to the I/O/power/ground ports they are protecting.
Figure 1 These are typical I/O ESD protection and cross-domain ESD protection circuits.
Selecting the correct connectivity scheme is crucial to ensure an ESD protection circuit will function as intended. Driven by the connectivity scheme, the layout geometrical/electrical property scheme of matched ESD devices is equally important to ensure adequate ESD protection. Both the individual and total strength of ESD devices must be evaluated.
Using the I/O ESD circuit in Figure 1 as an example, tracing from each I/O port shows that the negative pin of the pull-down diode, or the source-drain pin of an ESD-hardened NMOS MOSFET must be tied to the I/O port, and that the positive pin of the pull-down diode or the source/drain pin of an ESD-hardened NMOS MOSFET must be tied to the ground port. The gate pin of an ESD-hardened NMOS MOSFET must be directly connected to the ground port, or indirectly connected to the ground port through resistors. Finally, it’s important to ensure that the protection devices themselves are robust enough to do their assigned tasks. This is accomplished by analyzing the gate channel width/length of the MOSFET devices in use, and the area/perimeter of the pull-up and pull-down diode devices being used for ESD protection.
In some designs, where a secondary or charged device model (CDM) is used, ESD protection can include resistors, and another stage of active devices, either in the form of pull-up/pull-down diodes or PMOS/NMOS transistors. The ESD resistors may be placed in a cluster, with one end tied to the primary ESD protection circuit on the I/O net, and the other end tied to the secondary ESD protection circuit on the net connecting to the gate pin of the internal gate. The effective resistance of ESD resistors clustered between the I/O and internal gate nets must be analyzed by using SPICE to solve a matrix of connected resistors, with each resistor’s actual value calculated from its layout geometry and the bulk properties of the process node being used to fabricate the device.
ESD protection circuits between power and ground ports
It is also important to verify that every power clamping-purposed NMOS device, or series of cascaded NMOS devices tied to an RC trigger circuit, is connected to the ground port (Figure 1). For designs with multiple power domains, a B2B diode structure is generally required between common ground and local ground ports.
ESD protection circuits across different power domains
Cross-power-domain paths may have a CDM-style ESD susceptibility. These paths between functional blocks that are operated under different power domains, require an ESD protection circuit similar to I/O ESD protection, as shown in Figure 1. The process for identifying a cross-power-domain path is as follows: starting at the source/drain pin of a PMOS receiver gate that is connected to one power net, search to determine if the gate pin of this PMOS device is connected (possibly through resistors) to the source/drain pin of another PMOS device that is connected to another, different power net.
If such connectivity exists, the net or path between the gate pin of one PMOS device and the source/drain pin of another PMOS device is a candidate for a cross-power-domain net/path. The circuit used for these paths is similar to those used for I/O ESD protection. Both the connectivity scheme and the layout geometrical/electrical property scheme of matched ESD devices are equally important to ensure the ESD protection circuit functions as designed.
To limit the physical area required by the cross-domain ESD protection circuit, designers can identify the specific high-risk cross-power-domain paths that require this added ESD protection. Identifying these critical paths involves using additional criteria to examine the status of ground domains and power clamping protection between each power/ground pair.
Automated ESD verification methodology
Automated ESD rule checks are executed by starting from a group of user-defined nets and/or devices of critical interest for the associated ESD paths under examination. For the I/O ESD check example, the process first identifies all I/O nets to verify the logical elements in the design. Tracing along each I/O net, the attached devices are subject to certain connectivity constraints (including constraints on the device “type” and “subtype”). Once the correct design elements are selected, the next step is to perform the operation associated with these elements.
The applicable physical and/or electrical properties may be stored in the extracted layout netlist. If that is the case, then the logic-driven layout check can be accomplished using only the layout netlist. If the applicable physical properties are not stored in the layout netlist, then the devices and/or nets selected will require further analysis, this time on the actual design geometries they represent with appropriate physical layout measurements (DRC) made to extract the necessary physical properties. Figure 2 illustrates an overview of the logic-driven layout geometrical check methodology.
Figure 2 Here is an overview of logic-driven layout geometric check flow.
After it’s been determined that the required I/O ESD, power clamping, and cross-power domain ESD protection circuits are in place, shouldn’t there be a similar analysis of the interconnect wires between these circuits? This could be an issue in ICs fabricated at advanced process nodes, where the impact of interconnect parasitics can be significant.
The concern here is not just whether or not the ESD protection circuits exist, but about the parasitic effects of as-designed ESD paths along I/O and power/ground nets across the whole chip. ESD paths are usually from pad to pad (a pad is defined as the physical representative of a port). While an I/O port usually has one corresponding physical pad, a power or ground port can have one to many physical power or ground pads. For example, at the full-chip level, a typical ESD path can begin at an I/O port, connect through a cluster of ESD devices to one or more power clamping devices, and finally terminate at a power or ground port. Along a typical path, the power clamping devices may be clustered in many physical locations, each of them placed close to many other power or ground pads.
A single logical ESD path can devolve into many physical paths, each of them passing through a cluster of power clamping devices, and ending on a single power or ground pad, or grouped power or ground pads (depending on the designer’s preference). To ensure the ESD path functions as designed, it is critical to examine not only the placement of the related ESD circuits, but also the effective resistance along the ESD path. If the interconnect along an ESD path has high effective resistance, then the ESD path becomes ineffective. If high resistance prevents ESD energy from being completely diverted through the as-designed ESD current path, the internal functional circuits it’s supposed to protect will be vulnerable to an ESD event.
Measuring the effective resistance of an ESD path can be challenging. The task includes deriving each path from the layout database, and extracting huge power/ground resistance networks (R-networks). By using a logic-driven layout methodology integrated with parasitic extraction and simulation, the ESD current path’s effective resistance analysis can be determined as part of an automated rule check (as shown in Figure 3). The flow leverages an LVS extracted layout netlist from a (typically) GDS II/OASIS layout database for design topology traversal. Based on the connectivity scheme of the ESD and power clamping circuits, the I/O pad, ESD devices/pins, power clamping devices/pins, and power/ground pads are identified and used to form logical pin pairs (or point-to-point (P2P) segments) to construct ESD current paths.
Figure 3 Here is an overview of a logic-driven layout electrical check flow.
The parasitic R network is extracted, and the interconnect resistance of these paths is simulated to determine the effective resistance of the ESD paths. This resistance is then compared against a design rule constraint to determine if the specified criteria has been met.
Using the earlier I/O example, let’s consider an ESD path which begins at an I/O pad, runs through a cluster of ESD devices to a cluster of power clamping devices, and then terminates at a power or ground pad. Typically, a path like this will contain multiple P2P segments consisting of:
An example of these ESD paths’ P2P effective resistance measurements is shown in Figure 4.
Figure 4 These P2P effective resistance measurements are for an ESD path containing three P2P segments.
The “point” where the P2P measurement is made can be either a power, I/O, or ground pad, or a device’s pin/cell port. Each P2P segment is formed by pin pairs on the same net, and pin pairs can be exported with an annotation index for grouping purposes during simulation. The pin pairs are transformed into probe points which are stored inside a SPEF network. A static simulation is then run to solve the V=IR matrix equation, which calculates the effective resistance of the P2P segments that form the ESD path.
But even after this analysis demonstrates that the interconnect effective resistance of each ESD path is low enough to ensure it will function as designed, it is still possible that a very large ESD surge current (with different dynamic natures for different ESD modes) could damage a weak interconnect and lead to silicon failure. To help designers debug and locate the weak interconnect points at greatest risk from an ESD surge current, the current density through all wire segments and via arrays along ESD paths must be analyzed to ensure the current density is within a set tolerance range. The flow for measuring the current density along an ESD path is similar to the one used to measure the effective resistance of ESD paths. The main differences are in the specific values of the injected ESD current that correspond to either a CDM or a human body model (HBM). Figure 5 displays current density measurements in which the highlighted current density violates the defined limits per layer.
Figure 5 These current density results highlight a physical location with a current density higher than the defined criteria
Full-chip ESD protection verification is challenging, especially for designs intended to be fabricated using advanced sub-micron process nodes. Manual inspection is time- and resource-intensive, and its accuracy is affected by both human expertise and error. A rule-based, logic-driven, layout static approach can automate context-aware check methodology for full-chip ESD design verification.
This approach enables foundries to develop and provide qualified ESD process design kits that cover a majority of ESD rule checks for chip-level tape-out. Using these foundry ESD design kits and their own specialized ESD/reliability expertise, in conjunction with an EDA reliability verification tool that can apply logic-driven layout-based verification, design houses can implement an automated ESD verification flow to ensure their designs are adequately protected against ESD events. Automated context-aware chip-level ESD protection verification not only reduces time to tape-out, but also ensures that designs are robustly and consistently protected against operational failure due to ESD events.
Frank Feng is a circuit verification methodologist in the Calibre organization at Mentor, a Siemens Business.
Li Li is a senior technical marketing engineer supporting Calibre LVS, PEX, and PERC tools in the Design to Silicon division of Mentor, a Siemens Business.