Partition PCBs into analog and digital sections, but don't run signals across those gaps.
Part 1 of this series described how digital signals propagate through PC boards, and Part 2 described specific board stack-up designs to achieve low EMI. Part 3 will address partitioning of circuit sections, routing of high-speed traces, and a few other layout practices to help reduce EMI.
Besides proper layer stack-up, the next most important consideration when laying out the circuitry on your board is partitioning of circuit functions, such as digital, analog, power conversion, RF, and things like motor control or other high-power circuits.
Before we get to circuit layout, we must first understand and visualize how return currents flow and how the electromagnetic fields are distributed under high-speed circuit traces. At low frequencies—below about 50 kHz—return currents tend to follow the path of lowest resistance. They tend to travel along the shortest distance between source and load, as simulated by the green area in Figure 1.
At roughly 50 kHz to 100 kHz, return currents tend to follow the path of lowest impedance due to mutual impedance coupling effects between the signal path. These currents tend to travel directly underneath the signal path between source and load, as simulated by the green area in Figure 2.
You can now understand why analog circuitry should be located well away from digital or other noisy circuits. Keep these “spread out” return currents from intermixing with the return currents from noisy circuitry. That’s the main reason why partitioning is so important.
Part 1 of this series described how the digital (and other high-frequency) signals propagate through a board’s dielectric space. To avoid signal coupling and crosstalk, you must not allow the various return signals from intermixing within the same dielectric space. Thus, you need to partition major circuit functions. Figure 3 demonstrates one example of partitioning. Of course, this gets more challenging as board size shrinks. Henry Ott also describes this concept in Reference 1.
Knowing now that low frequency signal returns tend to spread out more, we can see that any analog or low-frequency circuitry must be separated from digital, power conversion, or motor controller circuits. Likewise, sensitive RF receiver circuits, such as GPS, cellular, or Wi-Fi devices must also be kept separate from digital, power conversion, or motor controller circuitry, as well.
Here are some guidelines to follow when routing signals on PCBs to minimize interference.
Gaps in Return Planes: All ground return planes (GRPs) should be as solid as possible and designed without long gaps or slots. As mentioned in Part 1, when a high frequency trace crosses a gap in the return path, this creates a source of common mode currents, which generally couple all over the board and create the potential for radiated emissions failures (references 2 and 3).
These common mode currents couple to power and I/O cables, which then radiate. But the gap also causes field leakage within the dielectric space, which can couple to nearby vias from other signals, causing unwanted coupling similar to crosstalk. It also causes “edge radiation” directly from the board. If the harmonic frequency of the common mode currents is 1/4 to 1/2 wavelength of either the cables or board dimension, they’ll act as transmitting antennas and radiate. See my video demo on “gaps in return planes” (Reference 4).
Via penetration: Very often, you need to run signals from the top side to the bottom side (or interior-to-interior layers), relying on vias to get there. If you only need to pass from one side of a GRP to the other, there’s no issue, because the electromagnetic field of the signal is contained along the entire path (Figure 5).
It’s only when you need to pass through multiple planes that you might fail to provide a return path for the electromagnetic wave as it travels through the dielectric space of the board (Figure 6).
If there’s no transmission-line continuity between the planes (stitching via or capacitor), then you will get field leakage throughout the dielectric space as the signal tries to find a way back to the source. This field energy will couple to other vias, as well as propagate out as “edge radiation.”
If the two planes are GRPs, then you need to merely stitch them together in at least one location near the signal via. This allows field propagation along the entire path. As I’ll mention later, a matrix of ground vias is always a good practice and if they’re located very close together (5 mm spacing is good), there’s no need to specifically locate one at each penetration.
If, however, the two planes are at different potentials, such as a GRP and power, then a stitching capacitor needs to be installed next to the signal via. If there are dozens of signal penetrations on such a board, it may be impractical to add a stitching capacitor for every signal penetration, so that’s one reason to locate an even distribution of decoupling/stitching capacitors throughout the board. This will also help reduce “ground bounce” or simultaneous switching noise (SSN).
Routed power versus power planes: The conventional method is to start with one or more (depending on the number of layers) power-ground “cores” and build the signal layers from there, usually equally on each side of the core for best manufacturability. Typically, digital ground return is used for this. Another big advantage is that when spaced very close together (less than 3 mils), the power-ground core becomes a good high-frequency decoupling capacitor. As the number of layers increase, it’s often best to locate two or more power-ground cores closer to the top and bottom of the stack-up—generally on layers 2-3 and 6-7 (on eight-layer boards, for example).
The disadvantage is that stitching (or decoupling) capacitors are required to maintain transmission lines for the signals passing through. Other voltage rails are then generally routed on signal layers.
There’s one big advantage with routing all power and using one, or more, GRPs. That is, all the GRPs can be stitched together in a matrix pattern and you won’t need dedicated stitching capacitors. Multiple GRPs, when located on outer layers, may be stitched together around the perimeter of the board to form a Faraday shield.
On the other hand, every digital device will need 2-3 decoupling capacitors per power pin, or tight groupings of pins. In addition, rails (typically the main digital voltages) should have wider pours around any high di/dt devices, such as core voltage, drivers, ASICs, motor controllers, processors, etc. This will help serve as your high frequency decoupling.
Routed triplets: In the case where you may not have a continuous GRP, such as some two-layer board designs, both analog and digital traces may be routed as “triplets”, with a single return trace located and routed along with two signal traces. This was described and illustrated in Part 2 and has been featured by Dan Beeker, of NXP Semiconductor (Reference 5).
Ground pours: It’s always a good practice to fill any spaces between signal traces with ground pours. These ground pours must be connected in multiple places to all GRPs within your board. This does two things; it provides additional shielding, as well as paths for signal returns, and it enables a better and reliable board design from a production standpoint.
Multiple ground vias: It’s a good practice to create a matrix of ground vias connecting all ground pours and GRPs together using a spacing of about 5mm. This will provide multiple return paths for signals penetrating more than one GRP layer. In addition, if you use multiple GRPs, you should design via stitching all around the periphery of the board to create a Faraday cage for those signal layers in between. This technique is especially important when incorporating wireless technology in the design.
Other guidelines to minimize EMI
Clock oscillators/crystals/drivers: Locate your clock oscillators towards the center of the board (or digital partition), as close to the device they’re driving, and away from board edges and especially, I/O or power connectors.
Clock traces: All clock traces should be short and direct. Avoid running these along board edges, because that can physically couple to the board edge and cause board resonances and consequent board radiation.
I/O and power connectors: If possible, locate your I/O and power connectors along a single edge of the board. The father apart one connector is located from another, the more EMI-related noise voltage can be measured between their connector bodies. What is a high frequency noise source between two long wires? A dipole antenna! You want to minimize the “noise” voltage drop between all connectors.
RF module transmission lines: All antenna transmission lines should be run short and direct to the antennas or antenna port connectors. These should be buried in between two GRPs and may dictate eight, or more, layers to achieve a 50-Ω impedance through “keep out” areas in the layers immediately above and below the transmission line(s).
In addition, add rows of via stitching, spaced every 3 mm to 5 mm, connecting all the GRPs along each side of every antenna transmission line. This will provide additional shielding.
Ethernet connectors: There should be a ground return plane “keep out” area directly underneath Ethernet connectors. This will help transition from single-ended signal pairs to balanced signal pairs.
90-degree turns: It’s been pretty well proven that for normal (to at least to several GHz) digital traces, it’s not necessary to chamfer or round off corners. It’s OK to make 90-degree bends where needed (References 6, 7, and 8).
20H Rule: There is also the so-called “20H Rule” where the power plane should be set back from the edge of the GRP by 20 times the layer thickness. This supposedly helped reduce fringing fields. If nothing else it simply makes the field lines longer (References 9 and 10).
I suspect there’s many more and perhaps readers could add to the list through their comments.