A guide to using FETs for voltage controlled circuits, Part 3

Article By : Ron Quan

This article on FETs for voltage controlled circuits will cover FET modulator circuits and VGA design via reducing the drain-to-source voltage.

Read Part 1 and Part 2 of this series.

This article on FETs for voltage controlled circuits will cover FET modulator circuits and variable gain amplifier (VGA) design via reducing the drain-to-source voltage.

FET modulator circuits

In Part 1 and Part 2 of this series, a DC voltage from a potentiometer provided the control voltage. However, the control voltage can include a DC bias and an AC signal, which then provides a time varying gain signal such as an amplitude modulated signal.

If we replace the potentiometer VR1 with an AC signal plus DC bias signal in any of the previous Figures 3 to 17, the voltage controlled attenuators can become an amplitude modulator circuit instead. For example, in Figure 15 (P Channel MOSFET) if the input signal, Vin, is a high frequency carrier signal and VR1’s signal, Vcont is replaced with a negative DC bias signal plus a low frequency sine wave signal, the output signal Vout will have an amplitude modulated carrier signal such as in Figure 18.

Note: The vertical axis denotes amplitude and horizontal axis denotes time in Figures 18, 19, 20, and 22.

Figure 18
An amplitude modulated (high frequency) carrier signal and its low frequency sine wave modulating signal.

In Figure 15 with a P Channel MOSFET, as the gate voltage approaches 0 volts, the drain-to-source resistance increases, allowing the voltage-controlled attenuator to pass the input signal to its output with minimum attenuation. Note that in the positive peak of the sine wave, the amplitude modulation signal is at its greatest amplitude.

Conversely, if the P Channel MOSFET’s gate voltage turns more negative, there is more conduction or less resistance across the drain and the source. Thus, there is a maximum attenuation that results in a minimum amplitude-modulated signal at the output. Now observe that the amplitude-modulated signal is at a minimum when the low frequency sine wave is at its negative peak.

We can describe the amplitude-modulated high frequency carrier, cos(2πft), signal as:

m(t) = modulating signal (e.g., a low frequency signal)

f = frequency of the “carrier” signal

Also, [ 1 + m(t) ] ≥ 0 such that cos( 2πft ) is multiplied by a non-negative scalar or number to ensure that there is no phase reversal or inversion of the high frequency carrier signal.

For example, a standard broadcast amplitude modulation signal looks like Figure 18 where the high frequency carrier signal always has an envelope that looks like the low frequency modulating signal.

In terms of standard types of amplitude modulation, there are other applications. These include a musical wavering effect for tremolo, and an automatic gain control amplifier for audio amplitude compression (not to be confused with data rate reduction via compression algorithms).

Now let’s take a look another type of amplitude modulator, which is characterized by “pure” multiplication.

[ m(t) ] cos( 2πft ) = Double sideband suppressed carrier signal (13)

Figure 19 shows what a multiplied carrier signal or double sideband suppressed carrier amplitude modulated signal looks like.

Figure 19
A multiplied carrier signal with its modulating sine wave below it.

Notice that the multiplied carrier signal does not exactly have a recognizable envelope like the one shown in Figure 18. Figure 20 further shows the relationship of the carrier signal’s phase.

Figure 20
A constant amplitude carrier signal is above the multiplied carrier signal with its modulating low frequency sine wave superimposed.

If you notice very carefully the phase of the high frequency modulated carrier signal has its phase reversed when the low frequency modulating signal is at its negative cycle. At the origin axes, we see that the modulating signal is in the positive cycle, and the amplitude modulated waveform is in phase with the carrier signal above.

Making an analog multiplier circuit is a bit more complicated than a basic standard amplitude modulator circuit such as Figure 15 that includes a DC bias voltage with an AC modulating signal for Vcont. An analog multiplier circuit generally requires two basic standard modulator circuits with a twist … the second circuit requires an inversion of both its carrier and modulating signals.

Let’s see how this is done:

[ 1 + m(t) ] cos( 2πft ) = AM signal #1

For the second AM signal, let’s invert the phase of both m(t) and carrier signal cos( 2πft ), such that:

[ 1 + m(t) ] (−1) cos( 2πft ) = AM signal #2 , but this is equivalent to:

[ -1 + m(t) ] cos( 2πft ) = AM signal #2

Let’s now add the two signals:

AM signal # 1 + AM signal #2 = [ 1 + m(t) ]cos( 2πft ) + [ −1 + m(t) ] cos( 2πft )

= [ 1 + m(t) + −1 + m(t)] cos( 2πft )

AM signal # 1 + AM signal #2 = [ 2m(t)] cos( 2πft ) ]

From above, we now have a multiplier function or circuit when both AM signal #1 and AM signal #2 are added. Figure 21 shows an example with two “standard” AM circuits summed to form a multiplier circuit.

Figure 21 An example multiplier circuit using a dual N Channel JFET for generating AM double sideband suppressed carrier signals.

In Figure 21, the AM signal #1 is implemented by (N Channel JFET) voltage-controlled resistor Q1A and amplifier U1B. Q1A’s drain-to-source resistance (Rds_Q1A) is lower when Vmod is at a positive peak compared to having its drain-to-source resistance being higher when Vmod is at a negative peak. Because with R13>> Rds_Q1A, U1B’s closed loop gain = 1 + R12/Rds_Q1A, we see that the gain for the carrier signal increases when the modulation signal increases and vice versa. Signal output from U1B’s pin 7 provides AM signal #1.

[Continue reading on EDN US: Implement AM signal #2]

Ron Quan is an author, design engineer, and inventor with over 75 US patents.

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