A guide to using FETs for voltage-controlled circuits, Part 5

Article By : Ron Quan

The conclusion of this series covers bias servo circuits and offers some final tips.

See Part 1, Part 2, Part 3, and Part 4 of this series.

The final part of this series will start with bias servo circuits for automatic set up. The FETs pinch off or threshold voltage can vary widely for the same part number. Depending on the fabrication wafer lot chosen, these voltages can vary 2 or 3 to one. To bias them correctly for a predetermined drain-to-source resistance, the user must hand-adjust and calibrate the bias voltage across the gate and source. We can more easily bias the gate to source voltage with a matched dual FET or matched quad FET array.  One FET from the dual or quad device is used as a reference for precisely biasing the gate of the remaining FET(s) for a predictable drain to source resistance.

With a bias servo circuit, the drain to source resistance is always set correctly regardless of which matched FETs are used. For example, if you set the bias servo circuit to provide a 10KΩ drain-to-source resistance, R_ds, you can plug in a different batch of dual FETs such as LSK489, LSK389, etc. and you will still have the same R_ds. See Figure 40, a Wah-Wah variable band pass filter circuit with a bias servo circuit.

Figure 40 Incorporating a feedback or servo biasing circuit, U3 and Q1B, provides the correct gate voltage to an FET for a known drain-to-source resistance.

By using a reference FET, Q1B with a small DC bias voltage, Vref = +100 mV DC and a known load resistor, R6, we can bias Q1B to any drain to source resistance, R_ds by setting the voltage to R8 via potentiometer VR2 pin 2. The small DC voltage, Vref is set to +100 mV DC to ensure that the Q1B is still in the triode or ohmic region. If we set VR2’s slider voltage = Vset to provide half the voltage, or +50 mV, this will cause the bias servo circuit to turn on Q1B until its drain voltage is also +50 mV DC. If we get half of the +100 mV = 50 mV at the Q1B’s drain via the 10KΩ series resistor R6, this means the drain to source resistance is also 10KΩ. Because the bias servo circuit is a negative feedback circuit whatever voltage we set at VR2’s slider, which is coupled to U3A’s (-) input, its (+) input must follow that voltage by the virtual short circuit across the input terminals. Since the (+) input terminal is connected to the Q1B’s drain, its drain voltage must match the voltage at VR2’s slider. Compensation capacitor, C5, ensures that the circuit does not oscillate. For better noise rejection, C5 can be as large as 1 uf.

With Vset = voltage at pin 2 of VR2, the general equation that solves for Q1A’s R_ds is:

When the reference voltage Vref is small like 100 mV, we should choose an op amp for very small input offset voltages. The TL082/TL062/LF353 op amps have maximum offset voltages of 10 mV, which is not recommended. An LF412 can be used, which has a lower 3 mV input offset voltage. Of course, other low offset voltage op amps can be used (Figures 41, 42, and 43).

Note: Diode D1 ensures that the reference FET’s gate does not forward bias during turn-on. If the gate does forward bias, the bias servo circuit may be “stuck.”

In terms of maximum input signal amplitude for low distortion, usually < 150 mV peak-to-peak will work. However, generally FETs such as the VCR 11 with a higher pinch off voltage can tolerate a higher input amplitude > 150 mV peak to peak.

Now let’s look at Figure 41, the Wah-Wah voltage-controlled band-pass filter with distortion lowering feedback via Rfb and R4 with a bias servo circuit.

Figure 41 Automatic bias approximation when feedback is employed with the voltage-controlled resistor.

Because the distortion-lowering feedback network Rfb and R4 has about a 50% attenuation to the gate, amplifier U3B is set for a gain of 2 to compensate for this. Note that R1 <<R4 so that this 50% approximation holds.

Although increasing the gate voltage of Q1B approximates the same R_ds for Q1A, the drain to source resistance of Q1A is actually lower for the same gate voltages of Q1A and Q1B. The reason is that the resistor network, Rfb and R4 forms a negative feedback effect that slightly lowers Q1A’s R_ds. That is R_dsQ1A < R_dsQ1B by a little.

Nevertheless Figure 41 still provides an easier way to bias the FETs when compared to doing it manually. We will revisit a more accurate way to Figure 41 later.

For now, let’s see a bias servo circuit for the phase shifting system in Figure 42. It uses the same bias servo circuit as in Figure 40, but this time with MOSFETs for the voltage-controlled resistors. Note that D1 is connected in reverse to ensure the gate to source voltage does not go too negative for the N Channel enhancement devices upon turn on.

Figure 42 A three stage phase shifting system with a bias servo system.

The total phase shift from this circuit is:

As an example, Vset = 0.033 v = voltage at pin 2 VR2, then

Note that –Vsub = −5 volts to −10 volts DC to ensure that the substrate is biased correctly.

Instead of using Vww, a modulating signal may be coupled to VR2 pin 2 with a 1000 uf electrolytic capacitor with its (+) terminal at pin 2 of VR2.

See Figure 43, an improved servo biasing circuit.

Figure 43 Improved servo biasing via replication of VCR’s feedback circuit for Wah-Wah circuit.

To determine more accurately the R_ds of Q1A, the bias servo circuit replicates the feedback network via U4A that “copies” U1A, and R10 with R9 that copies Rfb and R4.

We should also note that even though this circuit can more precisely set the correct gate biasing voltage, the actual drain to source resistance for Q1A will be slightly lower due to a negative feedback effect from Rfb and R4. So, we will use “∼” for approximately instead of “=”

The biasing is set by the VR2’s slider voltage at its pin 2, Vset such that:

Again, instead of using Vww, a modulating signal (< 20 mV peak to peak to ensure that the bias servo circuit is within its range for Vset) may be coupled to VR2 pin 2 with a 1000 uf capacitor.

Note: Lower distortion may be achieved by setting the FET’s drain to source resistance to a higher value. For example, we set R6 to 51KΩ instead of 10KΩ , and set R_{ds_Q1a} to be in the > 100KΩ range.

For P Channel JFET devices with Figures 41 and 43, use a negative Vref such as – 100 mV DC and reverse diode D1’s connections. And for P Channel MOSFETs using Figure 42, use a negative Vref such as – 100 mV DC and reverse diode D1’s connections.

[ Continue reading on EDN US ]

Ron Quan is an author, design engineer, and inventor with over 75 US patents.

Read the whole series:

• A guide to using FETs for voltage controlled circuits, Part 1
• A guide to using FETs for voltage controlled circuits, Part 2: N-Channel JFET attenuator circuit with feedback
• A guide to using FETs for voltage controlled circuits, Part 3: FET modulator circuits and VGA design
• A guide to using FETs for voltage controlled circuits, Part 4: Voltage-controlled phase and musical effects

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