IC packaging needs a new approach for design and verification at all levels to enable designers to manage processes in an efficient, repeatable, and automated flow.
For many applications, next generation IC packaging is the best path to achieve silicon scaling, functional density, and heterogeneous integration while reducing the overall package size. Heterogeneous and homogeneous integration offer a path to enhanced device functionality, faster time-to-market, and silicon yield resiliency.
Multiple integration technology platforms have emerged that allow for cost, size, performance, and power optimizations that satisfy the need of multiple markets, such as mobile computing, automotive, 5G, artificial intelligence (AI), augmented reality (AR) and virtual reality (VR), high-performance computing (HPC), IoT, medical, and aerospace.
However, these packages present unique challenges for traditional package design tools and methodologies. Design teams must work together to verify and optimize the entire system, not just the individual elements. Traditional IC packaging substrate design is typically very similar to a small-scale laminate and/or build-up based PCB. It is often manufactured by traditional PCB fabricators and usually designed with modified PCB tools.
In contrast, today’s advanced packages use manufacturing techniques, materials, and processes that have increasingly more in common with silicon foundry processes and require a new approach for design and verification at all levels.
One of the first challenges a design team must overcome is the accurate aggregation of substrates—which can be both active and passive—and discrete devices. These substrates and devices come from multiple sources and suppliers and, most likely, are available in multiple and often different formats.
Given the multiple data sources and formats, it is clear that a comprehensive verification flow is required—one that accounts for assembly-level physical verification, as well as more in-depth, system-level electrical, stress, and testability verification. Also needed are design tools that deliver fast, accurate, and automated flows to ensure that market schedules and performance expectations can be met. Ideally, these flows provide a single integrated process built around a 3D digital model, or digital twin, of the entire heterogeneous package assembly.
These next-generation IC packages need a next-generation design and verification solution that incorporate and support:
Digital twin for virtual prototype
Building a digital twin, virtual model of the 2.5D/3D heterogeneous assembly provides a comprehensive representation of the full system comprising multiple devices and substrates. The digital twin enables automated verification of heterogeneous assemblies beginning with substrate-level design rule checking (DRC) and expanding into layout versus schematic (LVS), layout versus layout (LVL), parasitic extraction, stress and thermal analysis, and, finally, test.
Figure 1 A true 3D digital twin virtual prototype is the blueprint of an entire device. Source: Mentor Graphics
Model construction requires the ability to aggregate data from different sources and in different formats into a cohesive system representation suitable to drive verification and analysis. Ideally, this is done using industry standard formats like LEF/DEF, AIF, GDS, or CSV/TXT files. Functionality should also exist in a way that automatically recognizes device and substrate interfaces without having to instantiate pseudo components. This allows for multi-designer asynchronous design and verification. That, in turn, ensures overall system success when all components are completed and integrated.
One of the primary benefits of the digital twin approach is that it serves as the golden reference to drive complete physical and electrical verification at every level of the design hierarchy. That eliminates using multiple, static spreadsheets to represent pin and connectivity information, replacing them with a full, system-level netlist in Verilog format.
The preservation and reuse of original data, such as a device’s Verilog description, is key. The biggest risk comes when translation or conversion occurs, such as with a schematic or spreadsheet. If this is done, the “digital thread” is immediately broken, and the risk for connectivity errors skyrockets.
A digital twin methodology also enables multi-domain and cross-domain integration. Bringing more complex advanced IC packages to market faster requires highly-integrated design and verification—from electronic substrate design to mechanical package heat spreader and PCB mounting hardware, including the inter-related aspects of electrical, thermal, test, reliability, and, of course, manufacturability. Without a system-level approach to design and verification, engineers risk experiencing costly respins or worse.
Synchronization of electrical and mechanical information is essential to ensuring that no physical violations occur when a package is placed within an enclosure or an entire system. The incremental exchange of data during design is fundamental to ensuring ECAD-MCAD compatibility and increased first pass success. It also aids in the creation of more robust designs while increasing productivity and achieving faster time to market.
It is extremely important that both the IC package designer and the custom heat spreader designer can visualize, explore, and optimize the integration, ideally as an asynchronous process that minimizes cross-domain interruptions.
Figure 2 The digital twin methodology enables multi-domain and cross-domain integration. Source: Mentor Graphics
Synchronization between package design and mechanical/thermal design is also a significant challenge to first-time-right success. Heterogeneous multi-substrate packages exhibit multiple chip-package-interactions, with one of the largest being the thermal dissipation of heat, especially non-linearly generated heat typical in such packages.
A typical approach to thermal management uses a heat spreader for heat transfer and dissipation. But a heat spreader is only as good as its design. For the heat spreader to be efficient and effective, it must be designed and simulated in conjunction with the package, not as an afterthought. Designing the entire package in 3D ensures efficacious heat transfer realization without significant design compromises.
Figure 3 This is a digital-twin-driven integrated heat spreader design. Source: Mentor Graphics
Both 2.5D and 3D stacking can create a variety of unintentional physical stresses, such as substrate warpage during mounting and bump-induced stress. Designers must be able to analyze a layout for stresses caused by such chip-package interactions and their impact on device performance. Once the package is nearing implementation completion, the accurate 3D packaging thermal model can be exported for inclusion in detailed PCB and full-system thermal analysis. This enables final tuning of the system enclosure and allows natural and/or forced cooling to be optimized.
Advanced IC packages bring many new challenges for signal integrity engineers and their design tools. Dies are mounted directly to the substrate, so the potential for substrate routing to on-die redistribution layer routing coupling is possible. Packages are no longer simple planar layer structures with easily modeled simple vias between metal layers. Instead, there can be multiple substrates of very different materials and properties. Analysis can be used successfully for a number of signal- and power integrity-related items.
In addition, there are a number of items that are challenging to simulate. These generally fall into the category of electromagnetic interference (EMI). While these return-path-created EMI issues can be analyzed and simulated, it’s normally not productive to do so. For example, in the case of a trace crossing a split in a plane, simulation setup and run times will be considerable, and all engineers will learn is that such situations are bad and should be avoided.
These issues are best identified through software-automated, geometry-based inspection and checking during design. These can be typically set up and executed in minutes, with issue areas clearly highlighted for remedial design action. Such a “shift left” approach prevents issues from being created in the first place, making EMI analysis more of a verification sign-off step.
The 2.5D and 3D heterogeneous designs typically use through silicon vias (TSVs), which are long vias extending through the die or substrate to connect the front and back side. These TSVs allow die and substrates to be stacked and directly interconnected. However, in addition to their own significant electrical characteristics, TSVs also have an indirect effect on the electrical behavior of devices and interconnects in their vicinity.
To accurately model a 2.5D/3D heterogeneous system, a designer needs tools that extract precise electrical parameters from the physical structure of these 2.5D/3D elements, which can then be fed into behavioral simulators. Utilizing the 3D digital twin model of the complete package assembly, designers can accurately extract the parasitics of these 2.5D and 3D models. Once the elements have been extracted correctly, using the appropriate methodology and process, they can be assembled into a system-level interconnect model and simulated to analyze performance and appropriate protocol compliance.
Scalability and range
Heterogeneous packaging technologies are more complex to design, fabricate, and assemble, potentially limiting their availability to all but the leading semiconductor companies and their bleeding-edge designs. Fortunately, the design and supply chain ecosystem can play a powerful role in enabling the democratization of such technologies, putting them within the reach of all designers and companies—just as the silicon foundry world did with process design kits (PDKs), which have become ubiquitous.
Automated IC verification is driven by design rules created by the foundry and provided in a PDK to design houses. EDA tool suppliers qualify their toolsets against these rules to ensure their verification tools produce proven, repeatable, signoff quality results. The purpose of a package assembly design kit (PADK) is similar to that of the PDK—facilitate manufacturability and performance using standardized rules that ensure consistency across a process.
Obviously, a PADK must include both a physical verification and extraction signoff solution, and it should also address thermal and/or stress sign-off solutions. All of these processes should be independent of any specific design tool or process used to create the assembly. In addition, a complete PADK must work across both IC and packaging domains, implying that the flow must support multiple formats. Finally, all of these verification processes must be validated by the package assembly/OSAT company.
The scale and complexity of advanced IC packages put immediate pressure on the designer and the design schedule, which often gets extended. An emerging popular approach to managing this is concurrent team design, where multiple designers simultaneously work on the same design across local or global networks, yet retain the ability to visualize all design activity without having to endure any onerous setup or process management.
Figure 4 Multi-user concurrent design can shrink design cycles and optimize resources. Source: Mentor Graphics
[Continue reading on EDN US: Precision manufacturing handoff]
Keith Felton is marketing manager for Xpedition IC Packaging solutions at Mentor Graphics.