This article covers fundamental concepts and key principles behind signal integrity in high-speed data systems.
Signal integrity is one of the main topics that many designers deal with in high-speed digital circuit design. It involves the quality degradation and timing errors of digital signal waveforms as the signals travel on the path from the transmitter to the receiver through interconnects like package structures, PCB traces, vias, flex cable, and connectors.
Today’s high speed bus designs, such as LpDDR4x, USB 3.2 Gen1/2 (5 Gbps/10 Gbps), USB 3.2×2 (2×10 Gbps), PCIe, and the upcoming USB 4.0 (2×20 Gbps) all communicate their data via serializer/deserializer (SerDes) channels that employ differential signaling for enhanced signal integrity. Despite this, they still experience significant signal degradation as the high frequency data flows between the transmitter and receiver. This series provides an overview of the fundamental concepts of signal integrity and introduces key principles behind the phenomena occurring in high-speed data systems, including skin effect, impedance matching, characteristic impedance, and reflection.
As mobile applications migrate to 5G services, both handsets and the infrastructure equipment that supports them will need to support dramatically higher data rates, in many cases multiple Gigabits per second (Gbps). In turn, IC makers must use advanced submicron processes (10nm to 7nm and even 5nm) that enable their chips to support both higher data rates and higher levels of integration. At each successive process node, the size of the features decreases, and the Ft increases (i.e. the maximum frequency of devices on the IC). At the same time, the delicate structures of nanometer-scale transistors force IC makers to move to lower operating core voltages (i.e. 0.9V, 0.8V, .56V, and possibly lower) as well as optimize power dissipation.
While today’s ICs can operate at these higher frequencies and lower supply voltages, they are subject to several phenomena that make transmitting and receiving high-speed data streams increasingly challenging. The reduced operating voltage shrinks the space between the upper and lower threshold levels for detecting a “1” and a “0”, while the higher frequency shortens the time slot in which a given data bit can be received (i.e. the “data valid window”). The space bounded by the voltages and times during which a received data bit can be assumed to be valid is known as the “data eye.”
With this in mind, it’s easy to see how higher frequencies and lower voltages result in a smaller data eye, thereby increasing the chances of a receiver misreading an incoming bit. This increases the stream’s bit error rate (BER), which in most applications requires the packet in which the faulty bit was detected to be re-transmitted. Retransmit events cause two problems. First, if they are too frequent, they can noticeably degrade the useable capacity of a channel. In addition, retransmit events cause the device’s controller to remain in its active mode for longer than necessary. While this is not a significant problem for mains-powered equipment, the added on time caused by retransmits can cause significantly higher power dissipation which, for phones, tablets, and other mobile equipment, reduces their operating time.
Figure 1 Higher frequencies and lower voltages result in a smaller data eye.
Using high-speed SerDes data channels introduces several challenges to a product’s design process that must be overcome, including signal attenuation, reflection, impedance matching, and jitter. The following section will look at why these signal degradations make it difficult for the receiver to interpret the information correctly, thereby increasing the chance of a data error.
Clock sampling within a data stream
At the receiver, the data is sampled at the edges of a reference clock. The bigger the eye opening, the easier it is to place the edge of the sample CLK in the middle of the received bit for sampling, where it’s most likely to be valid. If the data stream has any amplitude attenuation or jitter, or contains any artifacts due to reflection, it will reduce the height and/or width of the eye diagram. This “closure” effectively makes the data valid window and valid bit time much narrower, increasing the odds of an error at the receiving end.
Figure 2 The bigger the eye opening, the easier it is to place the edge of the sample CLK in the middle of the received bit for sampling.
With this in mind, let us consider how the high-frequency behavior of SerDes channel elements, such as PCB traces, cabling, and interconnects can be treated as a transmission line. As you will see shortly, this type of analysis provides a very clear picture of the transmission losses that occur in a system like a smartphone or a tablet.
High frequencies and transmission line effects
As a rule of thumb, engineers consider a signal to be “low frequency” if its wavelengths are much greater than the length of the wire or PCB trace, and the resistance of the channel’s PCB traces and interconnects is not frequency dependent. Under these conditions, the transmission line effects resulting from the interaction between the signal and its channel can be considered negligible.
Conversely, designs are considered to be “high frequency” when the signal’s wavelength is much less than the wire/PCB trace length. In this case, all of the traces’ physical properties and interconnect dimensions need to be controlled in order to produce a transmission line with a set of electrical characteristics that are suitable for the application at hand. Equation 1 describes the relationship between wavelength and frequency, as a function of the transmission line’s propagation velocity.
Designers need to begin treating interconnects as a transmission line when the trace length begins to approach or exceed 1/10 the wavelength of the signal’s highest frequency. At this point, the only way to understand the channel’s behavior is to model the traces using lumped elements and consider all the frequency dependent elements within the channel. This includes parasitic capacitances and inductances and their affects on signal attentuation.
Another way to decide at the frequency at which an interconnect should be treated as a transmission line is by considering the signal’s rise time (tr). In addition, the wavelengths of multi-Gbps SerDes signals are short enough that the interconnect traces in devices fabricated using most of the current sub-nm process nodes begin to approach the 1/10 λ criteria discussed earlier, and have extremely sharp rise and fall times. Under these conditions, a channel or an interconnect must be treated as a transmission line. When a SerDes signal passes through a channel, its BW and propagation characteristics are governed by the signal’s rise time.
Since the signals are electromagnetic waves, their speed of propagation is largely determined by the dielectric constant of the material surrounding it. The formula for the propagation speed is:
The velocity of wave for a lossless transmission in free space (dielectric constant of 1) is about 3 × 108 m/s and, as Equation 3 shows, it will vary as a function of the dielectric. As a result, a transmission line with a dielectric constant of 4 will cut the signal’s propagation velocity in half, to about 1.5 × 108m/s.
The difference between the speed of a wave traveling in free space versus a PCB will cause a delay between the two signals, usually referred to as propagation delay (Td). As shown in Equation 4, the value of Td will depend both on the dielectric values of the two mediums and the distance that the signal has to travel:
Td = distance traveled/ Vp(prop speed) Equation 4
Now, what happens when one signal (CLK) propagates in a PCB’s outer layer, while another signal (data) is traveling on one of the PCB’s inner layers? The CLK signal’s channel sees free space on one side and the PCB dielectric on the other, while the data signal is surrounded on both sides by PCB dielectric constant. How much of a difference does this make?
In many applications, the high-frequency signals have to travel through interconnects or flex cables as well as the PCB traces we’ve discussed. Both of these elements have different impedances and dielectric values than the PCB traces, which cause deviations of both amplitude and timing. These effects, and any additional loss caused by the reduction in velocity of the signal, crosstalk, or any energy absorbed by the dielectric material will create random deviations in both timing and amplitude, usually referred to as jitter.
Figure 3 Any additional loss caused by the reduction in velocity of the signal, crosstalk, or any energy absorbed by the dielectric material will create jitter.
Here is where the designers must use transmission line theory to match the flight times of the two signals. Since the data signal traveling in the inner PCB layer will propagate slower, we will have to shorten the length of the data channel to match the flight time of the CLK signal.
If we observe at a portion of a given conductor (designated C1) while a current I(t) is sent through it, Ampere’s law says that a magnetic flux will be generated, and that it will be proportional to the current flowing through the conductor.
If we only consider a single conductor, without any other conductors in near vicinity, then the flux lines (B1) will create circulating eddy current in the conductor C1 in a direction opposite the field B1.
Figure 4 This diagram shows the current redistribution caused by the skin effect.
If the current alternates in polarity, the eddy currents will create opposition to the reversals in current flow, thereby increasing the conductor’s AC impedance. This effect is greatest toward the conductor’s core, thereby driving the majority of the current toward its surface, creating what is referred to as the skin effect. As frequency increases, the skin effect confines the currents to a smaller portion of the conductor thickness, increasing its effective resistance and corresponding loss. The effects of this behavior can be calculated using Equation 5.
Figure 5 Signal loss is due to frequency and trace path.
Transmission line and characteristic impedance Zo
The voltages and currents within a transmission line travel together and are functions of both position (x) and time (t). The characteristic impedance (Zo) of a transmission line is frequency dependent and can be described as the ratio of the traveling voltage wave to a traveling current wave (Equation 6).
Figure 6 This diagram shows V and I in a transmission line.
Under ideal conditions, the phases of the voltage V(x,t) and current I(x,t) waves are not disturbed and reach the termination impedance in synch. If there are no other complicating factors, Ohm’s law requires that V(x,t)/I(x,t) be equal to the termination impedance (ZL).
Figure 7 If there are no other complicating factors, Ohm’s law requires that Zo be equal to ZL.
In part 2 of this series, we will look at how real-world issues, such as parasitics and impedance mismatches, require additional analysis, modeling, and compensation.
Majid Dadafshar is principal engineer of Field Application Engineering at ON Semiconductor.