This article focuses on real-world signal integrity issues that require additional analysis, modeling, and compensation.
In Part 1, we explored the basic characteristics governing high-speed SerDes channels. This article focuses on real-world issues, such as parasitics and impedance mismatches, that require additional analysis, modeling, and compensation.
The simple situations described in the first part of this series are rarely seen in real-world applications. Things get more complicated when high frequency signals pass through non-ideal paths such as a PCB via, which serves as a conductor from one PCB layer to another, creating a change in impedance.
Figure 1 illustrates the layers, traces, and vias typically found in PCBs. In addition to the impedance changes at each transition, the signals are affected by the parasitic effects of both self and mutual capacitance and inductance.
Figure 1 These are the layers, traces, and vias typically found in PCBs.
For many applications, we can create a model that accounts for these effects using a technique called “lumped elements,” which attempts to capture the combined parasitic inductances, capacitances, AC skin resistance, and DC resistance that are present in any system (Figure 2). Parasitic capacitance (Cdx) can alter the channel’s current distribution, causing the characteristic impedance of the transmission line to be altered, which in turn causes the Zo (the ratio of the traveling voltage to traveling current) to change.
Figure 2 The lumped elements technique attempts to capture the combined parasitic inductances, capacitances, AC skin resistance, and DC resistance.
Figure 3 illustrates how as the skin effect reduces the amplitude of the incoming signal, the parasitic inductances present in the channel can degrade the rise and fall time of the voltage across the load. Unless they are somehow compensated for, these parasitic effects degrade the sharp edges of clock and data signals that receiver circuits need to accurately reconstruct them.
Figure 3 Parasitic effects degrade the sharp edges of clock and data signals.
Voltage reflection coefficient
As a high-frequency signal passes between different channel elements, such as from a PCB trace to a via, and then back to a trace on a different PCB layer, there will be a change in the impedance it sees at each transition. By controlling these parasitic effects and properly terminating the transmission line, it can carry signals with minimum distortion.
When the termination impedance (ZL) is not equal to the characteristic impedance of the line (Zo), it creates a pair of reflected voltage and current waves which combine with the source signal, thereby distorting it.
Note that when ZL is equal to Zo, the voltage reflection coefficient is equal to zero. This indicates that all of the incident wave is absorbed by the matched load termination (i.e. all the transmitted energy is received). When the signal’s voltage and current waves travel together and reach the termination impedance in their proper phase relationship, the total incident wave plus any reflected waves of V/I has to be equal to ZL.
Figure 4 When the signal’s voltage and current waves travel together and reach the termination impedance in their proper phase relationship, the total incident wave plus any reflected waves of V/I has to be equal to ZL.
Impedance mismatches and reflections
To understand the effect of impedance matching and mismatching, let’s consider a 50 ohm transmission line, terminated with 150 ohm termination impedance or an overdamped circuit (Figure 5). For simplicity’s sake, we shall set the impedance of the battery at zero, which drives the reflected wave back toward the load. For this example, let’s set the time delay (td=distance/Vp) for the wave to travel a given length. Now, let us close the switches and see what happens at the load.
Figure 5 Looking at a sequence of successive reflected waves will help us understand the effect of impedance matching and mismatching.
The waveforms in Figure 6 illustrate how the series of waves generated by successive reflections between the source and the termination impedance combine with and degrade the source signal, while also creating ringing on the signal line.
Figure 6 The waveform shows that the reflection causes ringing.
When calculating the reflection coefficient at both the termination and the source, we can determine the amount of incident wave that will reach the termination, as well as the amplitude of the wave that will be reflected back toward the source.
It is important to know these values since over-shoot ringing can produce higher voltages that may overstress electronic devices, or produce more radiated emissions that generate more crosstalk between neighboring traces. Under-shoot can be caused by either ringing or by a dip in the voltage rail during the transient response period. Either of these will increase the channel’s probability of a higher bit error rate.
For many mobile applications, a total loss budget, calculated in dB, that combines all the interconnect channel losses can be a valuable tool for understanding a design. The loss budget includes anything in the path from the silicon to the connector like silicon package, PCB traces, vias, flex, common mode filter, and connector. For this example, we’ll use a USB 3.1 Gen 2 channel, operating at 10 Gbps.
In order to maintain good signal quality without limiting the size of the PCB and placement of devices, employing re-drivers to boost signals that must traverse long channels is the most cost-effective solution. In a typical application, such as a smartphone or a tablet, the high USB connection’s high-speed signals travel from the APP processor’s package and pins to the PCB traces, and then through vias, connectors, flex cable, and the USB connector, each with its own impedance mismatch. As a result, the signals may already be degraded before going through an external USB cable.
Figure 7 This diagram shows typical signal paths and signal degradation.
As signals propagate through a channel, they experience attenuation and, depending on the length of the channel, it could be large enough to result in signal integrity issues at high data rates. This type of loss can usually be compensated with a re-driver, a signal-amplifier/conditioning device that can recover a signal that has become too weak. By boosting the signal’s amplitude, and sharpening its rising and falling edges, it allows it to travel further and lower its bit error by opening the eye.
Figure 8 Using a re-driver improves the opening of the eye.
Re-drivers are usually equipped with programmable differential output voltage levels that help align the drive strength with the line impedance and trace length, and equalize the signals. Keep in mind, however, that while increasing the drivers’ differential output voltage amplitude will help improve the received signal, it also increases noise and jitter.
Maintaining an acceptable signal integrity requires a careful attention to skin effect, matching terminations, reflections, vias, crosstalk, couplings, and their effects on signal attenuation. Any interconnect should be considered a transmission line when the length of the trace is around 1/10 of the signal wavelength.
Factors that contribute to signal integrity, like channel loss and signal reflections caused by impedance mismatch, occur during any data transfer from the processor though PCB, via, flex to cable, and vice versa. It’s vital for the interface to maintain impedance matching throughout the signal path to prevent reflections and provide maximum power transfer. Any impedance mismatch will cause reflections on the line, which will increase jitter and potentially compromise signal quality.
Without a re-driver, it would be very difficult or near impossible to pass system electrical and protocol compliance testing at data rate >10 Gbps. When testing for both short and long channel testing not having a re-driver, the total transmission channel distance for a given signal with high data rate can be limited with lower chance of interoperability among different devices.
— Majid Dadafshar is principal engineer of Field Application Engineering at ON Semiconductor.