Accounting for sampling clock jitter in data acquisition applications

Article By : Lloben Paculanan and John Neeko Garlitos

System designers need to take into account the error introduced by sampling clock jitter in their data acquisition applications.

Many data acquisition (DAQ) applications require an isolated DAQ signal chain path for robustness, safety, high common-mode voltage, or to eliminate ground loops that can introduce an error into a measurement. ADI’s precision, high speed technology enables system designers to achieve high AC and DC accuracy with the same design, without having to trade off DC accuracy for higher sampling rates. However, to achieve high AC performance, such as signal-to-noise ratio (SNR), the system designer needs to take into account the error introduced by jitter on the sampling clock signal or convert-start signal that controls the sample-and-hold (S&H) switch in the ADC. Jitter on the signal controlling the S&H switch becomes a more dominant error as the signal of interest and sample rates increase.

When the DAQ signal chain is isolated, the signal for controlling the S&H switch typically comes from the backplane for multichannel, synchronized sampling. It is crucial that a system designer selects a digital isolator that has low jitter so that the resultant control signal going to the ADC’s S&H switch has low jitter. LVDS is the preferred interface format for precision, high speed ADCs because of the high data rate requirements. It also creates minimal disturbance on the DAQ power and ground planes. This article will explain how to interpret the jitter specifications on Analog Devices’ LVDS digital isolators and which specifications are important when interfacing to precision, high speed products such as the ADAQ23875DAQ µModule® solution. The guidance outlined in this article is applicable when using other precision, high speed ADCs with an LVDS interface. The approach for calculating the expected impact on the SNR will also be explained in the context of the ADAQ23875 when used in conjunction with the ADN4654 gigabit LVDS isolator.

How Jitter Impacts the Sampling Process

Figure 1 shows the typical output frequency spectrum of a nonideal oscillator with the noise power in a 1 Hz bandwidth as a function of frequency. Phase noise is defined as the ratio of the noise in a 1 Hz bandwidth at a specified frequency offset, fm, to the oscillator signal amplitude at the fundamental frequency, fo.

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Figure 1. Oscillator power spectrum due to phase noise.

The sampling process is a multiplication of the sampling clock and the analog input signal. This multiplication in the time domain is equivalent to convolution in the frequency domain. Therefore, during ADC conversion, the spectrum of the ADC sampling clock is convolved with the pure sine wave input signal, and, thus, jitter on the sampling clock or phase noise will appear in the FFT spectrum of the ADC output data, as shown in Figure 2.

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Figure 2. The effect of sampling an ideal sine wave with a phase noise sampling clock.

Isolated Precision, High Speed DAQ Application

An example of an isolated precision, high speed DAQ application is a multiphase power analyzer. Figure 3 illustrates the typical system architecture with channel-to-channel isolation, and a common backplane for communication with a system compute or controller module. In this example we selected the ADAQ23875 precision, high speed DAQ solution due to its small solution footprint—making it easy to fit multiple isolated DAQ channels in a small form factor, thus reducing the weight of a mobile instrument for field testing use cases. The DAQ channel is isolated from the main chassis backplane by an LVDS gigabit isolator (ADN4654).

Isolating each of the DAQ channels enables each channel to be connected directly to sensors with significantly different common-mode voltages without damaging the input circuitry. The ground of each isolated DAQ channel tracks the common-mode voltage with a certain voltage offset. Enabling the DAQ signal chain to track the common-mode voltage associated with the sensor eliminates the need for the input signal conditioning circuitry to accommodate large input common-mode voltages and remove that high common-mode voltage for the downstream circuitry. The isolation also provides safety to the user and removes ground loops, which can impact the measurement accuracy.

Synchronizing the sampling event across all DAQ channels is crucial in a power analyzer application because mismatch in the time domain information associated with the sampled voltage will impact the follow-on calculations and analysis. To synchronize the sampling event across channels, the ADC sampling clock comes from the backplane through the LVDS isolator.

In the isolated DAQ architecture shown in Figure 3, the following jitter error sources contribute to the total jitter on the sampling clock controlling the S&H switch in the ADC.

1. Reference Clock Jitter

The first source of sampling clock jitter is the reference clock. This reference clock passes through the backplane to connect to each isolated precision, high speed DAQ module and other measurement modules plugged into the backplane. It serves as a timing reference for the FPGA; thus, the timing accuracy of all the events, digital blocks, PLL, etc. inside the FPGA are dependent on the reference clock’s accuracy. In some applications without a backplane, an on-board clock oscillator is used as a reference clock.

2. FPGA Jitter

The second source of sampling clock jitter is the jitter added by the FPGA. It is important to remember that there’s a trigger-to-execution path inside the FPGA, and the jitter specification of the PLL and other digital blocks inside the FPGA contribute to the overall jitter performance of the system.

3. LVDS Isolator Jitter

The third source of sampling clock jitter is the LVDS isolator. LVDS isolators have additive phase jitter that contributes to the overall jitter performance of the system.

4. ADC’s Aperture Jitter

The fourth source of sampling clock jitter is the ADC’s aperture jitter. This is inherent to the ADC and defined on the data sheet.

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Figure 3. Channel-to-channel, isolated DAQ architecture.

There are reference clock and FPGA jitter specifications that are given in terms of phase noise. To calculate the jitter contribution to the sampling clock, the phase noise specification in the frequency domain needs to be converted to a jitter specification in the time domain.

Calculating Jitter from Phase Noise

The phase noise curve is somewhat analogous to the input voltage noise spectral density of an amplifier. Like amplifier voltage noise, low 1/f corner frequencies are highly desirable in an oscillator. Oscillators are typically specified in terms of phase noise, but to relate phase noise to ADC performance, the phase noise must be converted into jitter. To make the graph in Figure 4 relevant to modern ADC applications, the oscillator frequency (sampling frequency) is chosen to be 100 MHz for discussion purposes, and a typical graph is shown in Figure 4. Notice that the phase noise curve is approximated by several individual line segments, and the endpoints of each segment are defined by data points.

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Figure 4. Calculating jitter from phase noise.

The first step in calculating the equivalent rms jitter is to obtain the integrated phase noise power over the frequency range of interest—that is, the area of the curve, A. The curve is broken into several individual areas (A1, A2, A3, and A4), each defined by two data points. The upper frequency range for the integration should be twice the sampling frequency, assuming there is no filtering between the oscillator and the ADC input. This approximates the bandwidth of the ADC sampling clock input. Selecting the lower frequency for the integration also requires some judgment. In theory, it should be as low as possible to get the true rms jitter. In practice, however, the oscillator specifications generally will not be given for offset frequencies less than 10 Hz or so—however, this will certainly give accurate enough results in the calculations. A lower frequency of integration of 100 Hz is reasonable in most cases if that specification is available. Otherwise, use either the 1 kHz or 10 kHz data point. One should also consider that the close-in phase noise affects the spectral resolution of the system, while the broadband noise affects the overall system SNR. Probably the wisest approach is to integrate each area separately and examine the magnitude of the jitter contribution of each area. The low frequency contributions may be negligible compared to the broadband contribution if a crystal oscillator is used. Other types of oscillators may have significant jitter contributions in the low frequency area, and a decision must be made regarding their importance to the overall system frequency resolution. The integration of each individual area yields individual power ratios. The individual power ratios are then summed and converted back into dBc. Once the integrated phase noise power is known, the rms phase jitter in radians is given by:

and dividing by 2πf0 converts the jitter in radians to jitter in seconds:

See “MT-008 Tutorial: Converting Oscillator Phase Noise to Time Jitter” for further details.

In the second article in this two-part series, we complete the discussion on error introduced by jitter by exploring how to quantify jitter in the reference clock, FPGA, digital isolation, and ADC aperture, then how to calculate overall jitter performance.

[Image source for all figures in this article is Analog Devices.]

This article was originally published on Embedded.

Lloben Paculanan is a product applications engineer at Analog Devices in GT, Philippines. He joined Analog Devices in 2000 where he worked in various test hardware development and applications engineering roles. He has been working on precision, high speed signal chain µModule development. He graduated from Ateneo de Cagayan Xavier University with a bachelor’s degree in industrial engineering technology and from Enverga University with a bachelor’s degree in computer engineering. He can be reached at

John Neeko Garlitos is a product applications engineer for signal chain μModule solutions at Analog Devices. He works on signal chain µModule development, as well as embedded software for Circuits from the Lab and reference circuits. He started working at Analog Devices in 2017 in GT, Philippines. He received his B.Sc. in electronics engineering from Technological University of the Philippines – Visayas, and M.Eng. in electrical engineering from University of the Philippines Diliman. He can be reached at


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