Circuit to limit voltage to a maximum of 1.5 V across dissipation limited devices with symmetrical limiting and a 2 A current rating.
I need a circuit to limit the voltage across some dissipation limited devices. It must: limit the voltage to a maximum of 1.5 V, have symmetrical limiting, be capable of accepting a current of 2 A, and leak less than 100 µA at 1 V.
Two Zener diodes in series, anode to anode, would do the trick, but Zener diodes with Vz = 0.8 V and a 2 W dissipation are not commercially available.
I searched the web to find what was available. In EDN’s design ideas webpage, I found one , however the circuit cannot limit voltages lower than 2.5 V. In another design idea  again, the minimum voltage of 1.8 V is too high for my application, but the current goes up to 6 A. Another reference  uses a single part that limits at 1.5 V, but its resistance is about 1 Ω and that combined with my requirement of 2 A will give too high a voltage. Another circuit  depends on the MOSFET characteristics to set the limit voltage and in my application that is not an option as I would have to test and select MOSFETs to find acceptable limit voltages. Finally,  offers a voltage range that is perfect with a maximum current of 8 A, but the off current is 200 µA and this is twice my limit. In conclusion: I have to design a circuit to suit my needs.
The circuit of Figure 1 has the needed characteristics. It is a modified shunt type voltage regulator. In this application, the voltage to be regulated comes from an external source, battery BT, in the schematic.
Figure 1 Schematic of a simple positive shunt voltage limiter.
Let’s say that the reference voltage, Vref_in in the schematics, is 1.5 V and that the voltage at the circuit output is also 1.5 V. Since both inputs to U1 are the same, the op amp output is 0 V, the MOSFET is off and no current flows through it. If the external voltage rises, the op amp output will become more negative and turn on Q1, a P-channel MOSFET, used in a source follower configuration, and more current flows in D1 and Q1. When the circuit is limiting, the impedance seen at the output is approximately the sum of the diode resistance plus Q1’s RDS(on) divided by the open loop voltage gain of U1. The output impedance is in the hundreds of milliohms range. Resistor R1 is a gate stopper resistor to eliminate the risk of oscillations in the MOSFET.
When the output voltage goes lower than the reference voltage, U1 output will rise positive and Q1 will enter the weak-inversion or subthreshold region . The feedback loop then becomes open and the op amp will saturate to the most positive voltage it can supply. Diode D1, blocks any reverse current that would flow through Q1’s body diode if the voltage at the output terminal goes negative. With the voltage at the output is below the limiting voltage, the current that flows in the circuit output is the sum of D1 reverse leakage and U1 input bias current.
Resistor R2 protects U1 in case of a negative overvoltage and allows loop compensation to take action via C1 by isolating the op amp inverting input from the output. The value of C1 is dependent on the op amp, the MOSFET and the layout.
Maximum rated current is defined as the current that makes the total voltage drop across the diode and the MOSFET equal to the reference voltage. The equation is:
Where VREF is the reference voltage (Vref_in), Vf is the voltage drop across D1 at the rated current, RDS(on) is the MOSFET maximum drain-source resistance and Imax is the maximum current available from the source. If more current than Imax is applied, the output voltage rises linearly from the set limit. If too high a current is applied, either D1 or Q1 will overload or overheat, resulting in permanent failure. Depending on the MOSFET used, maximum current can also be limited by the op amp maximum output voltage.
Actual measurements are listed in Table 1. All measurements were taken with a Vcc of +15.5 V and a Vee of ‑15.5 V because those are the target instrument supply voltages. To get good results, care should be taken as to where the voltmeter is connected during measurements; a four wire Kelvin connection and a stable reference voltage source are a must.
Table 1 Measurements taken for the circuit in Figure 1.
An current versus voltage curve for circuit in Figure 1 is shown in Figure 2. The circuit holds the voltage to within 1 mV of the reference while the current varies from 3 µA to 3 A. The knee is very sharp.
Figure 2 Current versus voltage for circuit in Figure 1, high current, note the square knee.
In Figure 3, the low current portion of the curve is shown; the total current range is almost 170 dB. The current is below 100 nA for most of the range between -14 V and +1.5 V. We can see that when the voltage reaches negative 14 V, current increases. The increase in current is because the voltage is getting close to the common voltage range limit for this op amp.
Figure 3 Current versus voltage for circuit in Figure 1, low current, showing current increase when nearing common mode range limit.
The circuit uses commonly available parts. Diode D1 and MOSFET should be selected to carry the full current and have a total voltage drop less than the reference voltage at the maximum current. Depending on the current value, the MOSFET may need heatsinking. I used a Schottky diode for D1, but a silicon p-n diode would do also. Since the input bias current of U1 flows from the output, I used a JFET input op amp; any low bias current op amp will work.
For symmetrical applications, the circuit of Figure 4 works well. It is made up of the positive limiter already seen and a complementary negative limiter connected in parallel. A single positive reference voltage is used to control both voltage limits. The negative reference voltage is generated by a unity gain inverter, U1.
Figure 4 Schematic for a symmetrical shunt voltage limiter.
Static measurements are in Table 2 and Figure 5 is the corresponding graph. Figure 5 shows symmetrical voltage limiting.
Table 2 Measurements taken for the circuit in Figure 4.
Figure 5 Curve for circuit in Figure 4, limiting voltage is very symmetrical about 0 V.
Since the op amp is in saturation when the circuit output voltage is below the limit, the response is slow. In Figure 6, a square wave was provided by a generator set to produce an open circuit peak to peak voltage of 4 V. The generator has 50 ohms output impedance. The oscilloscope CH1 is the circuit output voltage and CH2 is the op amp output. It takes about 20 µs for the op amp to slew 20 volts from approximately +15 V to -4 V.
Figure 6 Waveforms for circuit in Figure 4, shows slewing is the major limit to response. See text for details.
An improved circuit which does not saturate the op amp is in Figure 7. The main op amps U2A and U2B are now unity gain inverting amplifiers. Diodes D3 and D4 limit the op amps output voltage to 0.7 V in saturation . Op amp U2A output now has to slew only from +0.7 V to -4 V. Since the input resistor R3 will load the output, it is selected to be twice the minimum acceptable resistance specified of 200 kΩ, I had 499 k 1 % resistors on hand, so I used those. Waveforms are taken using only the positive limiter part from Figure 7, with 200 k resistors for R3 and R7.
Figure 7 Schematic symmetrical shunt voltage limiter with the final op-amps operated in inverting mode.
In Figure 8, oscilloscope CH1 is the circuit output voltage and CH2 is U2A output. The response is 5 µs, about four times faster than with the initial circuit.
Figure 8 Response time for circuit in Figure 7, bounded voltage leads to shorter slewing time. See text for details.
Table 3 and Figure 9 outline static measurements very similar to the first circuit, except that the current below VREF is in the microamperes range. To have asymmetrical limiting, remove the inverter stage and use two reference voltage sources.
Table 3 Measurements taken for circuit in Figure 7.
Figure 9 Curve for positive half only of circuit in Figure 7, increased speed does not affect DC performance.
If you need to limit the voltage to a value lower than 700 mV, the voltage lost in the diode will make it almost impossible to meet that requirement with either circuit. But if you connect the P-channel MOSFET drain to a negative voltage source, then any voltage limit is possible even 0 V. The same approach can be used for the N‑channel MOSFET. The circuit in Figure 10 does just that with performance comparable to the circuits above. The offset voltage source, battery B1 in schematic, should be capable of supplying the required current.
Figure 10 Schematic of a voltage limiter capable of operating below 1 V.
Table 4 gives the results with a 150-mV reference and an offset power supply of 1.8 V. Current versus voltage curves at high current, up to 1 A, are graphed in Figure 11. Here again the circuit shows sharp knee, low leakage and constant limiting voltage. The same technique can be used with the schematic in Figure 7. For limiting voltage values below approximately 1 V, error budget calculations should govern your selection for the op amps offset voltage and bias current maximum values.
Table 4 Measurements taken for circuit in Figure 10.
Figure 11 Curve for circuit in Figure 10.
This circuit could be used as a teaching aid, set the limit voltage to zero and insert the circuit in a test circuit for students. Imagine the fun and puzzlement of having a short circuit for one ohmmeter polarity and an open circuit for the opposite polarity!
For best results in high current applications, the voltage limiter should be installed between the voltage source and the device to be protected.
I tested various diodes: Zener, silicon PN, Schottky barrier and LEDs, and none of these have such a sharp knee, low leakage and can carry as much current or are as flexible in use as the above circuits.
With simple modifications, the clamping voltage could be extended to higher values, but that is another design idea.
 Peter Demchenko, Shunt circuit clips large transients or regulates voltage, https://www.edn.com/shunt-circuit-clips-large-transients-or-regulates-voltage/.
 Chris Toliver, High-power shunt regulator uses BJT & reference IC, https://www.edn.com/high-power-shunt-regulator-uses-bjt-reference-ic.
 Adolfo Mondragon, Power Zener using the LM317. https://www.edn.com/power-zener-using-the-lm317.
 Stuart R. Michaels, MOSFET shunt regulator substitutes for series regulator, https://www.edn.com/mosfet-shunt-regulator-substitutes-for-series-regulator/.
 Robert N. Buono. High-Current, Low-Voltage Shunt Regulator, https://www.electronicdesign.com/technologies/analog/article/21756712/highcurrent-lowvoltage-shunt-regulator.
 Sansen, Willy. M. Analog Design Essentials. ISBN-13: 9781489978912, page 24.
 Pease, Robert. «Bounding, clamping techniques improve circuit performance». EDN, November 10, 1983. Pages 277 to 289.
This article was originally published on EDN.
Daniel Dufresne is a retired engineer and has worked in telecommunications, mass transit, consumer products, high power electronics and custom instrumentation design. He also was a professor at Cegep de Saint-Laurent and taught courses at Ecole Polytechnique de Montreal. He lives in Montreal, Canada and still works on electronic projects and test equipment modifications and repairs.
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