ADC IP core bolsters calibration, linearity
Article By : Majeed Ahmad
The 10-bit SAR ADC IP core for SoCs reduces harmonic and intermodulation distortions at high output frequencies and amplitudes.
A new ultra-low-power analog-to-digital converter (ADC) IP core claims to reduce harmonic and intermodulation distortions at high output frequencies and amplitudes. The 10-Bit 3-Msps Ultra Low Power SAR ADC IP Core unveiled by T2M is silicon proven and it’s available for licensing.
The mixed-signal IP core features a 10-bit resolution and a 3-Msps sample rate; it also provides an optional differential current output or differential voltage output. Next, the analog IP core can be configured to adjust the full-scale output range and has all the necessary calibration circuitry to provide robust static and dynamic linearity performance.
Source: T2M
A digital signal, discrete in both time and amplitude, is created from an analog signal that is made continuous in both time and amplitude by an ADC. Its ultra-low area and power also facilitate accurate charge transfer without needing calibration. That, in turn, increases ADC channel speed and relaxes op-amp gain, bandwidth, and offset requirements.
The 10-Bit 3-Msps Ultra Low Power SAR ADC IP Core is targeted at microcontrollers, medical applications, and general-purpose ICs. According to T2M, it has already been used in medical, Ethernet, automotive, communication, and sensor applications.
This article was originally published on Planet Analog.
Majeed Ahmad, Editor in Chief of EDN and Planet Analog, has covered electronics design industry for longer than two decades. During this period, he has worked in various editorial positions, including assignments for EE Times Asia and Electronic Products. He holds a Masters’ degree in telecommunication engineering from Eindhoven University of Technology.