Advanced techniques such as FOWLP allow increased component density as well as boost performance and help solve chip I/O limitations.
Moore’s Law in process technology is on its last legs, so advanced packaging is taking up the baton. Advanced techniques such as fan-out wafer-level packaging (FOWLP) allow increased component density as well as boost performance and help solve chip I/O limitations. The essential key to successfully using such techniques, however, is to include the package in the chip design from the start.
For decades, semiconductor processing technology has steadily pushed feature sizes down from tens of microns to single-digit nanometers, effectively doubling component density every 18 months along the way. At the same time, however, design and fabrication costs have risen, threshold margins have narrowed, and a host of other challenges have appeared to impede further progress. Furthermore, increased transistor density in individual chips has created problems in connecting chips together, such as limiting IO pin count and the speed of chip-to-chip interconnects.
These limitations are proving especially problematic in applications such as artificial intelligence (AI) edge and cloud systems that need massive amounts of high-bandwidth memory. To address these issues as well as to continue improving component density, the industry has developed several advanced packaging technologies that allow multiple chips to interconnect in a compact, high-performance package that functions on a board as a single component.
One such technology, FOWLP, is already used in volume production for mobile devices. The FOWLP packaging process involves mounting individual chips on an interposer substrate called the redistribution layer (RDL), which provides the interconnections between chips and with the IO pads, all of which is packaged in a single over-molding.
Face-up and face-down approaches
There are several variations of FOWLP, each one using slightly different fabrication steps, available from a variety of vendors (Figure 1). The FOWLP assembly can be created using a mold-first process, with chips mounted face down or face up, or using an RDL-first assembly.
Figure 1 Variations in FOWLP technology include mold-first and RDL-first assembly options. Source: Micromachines
In the mold-first approach, chip die attaches to a carrier using a temporary bonding or thermal release layer, which is then molded into a package. If the die is attached face down, the next steps are to release the temporary layer, attach the RDL, and form the solder balls that complete the package. If the die is attached face up, some additional steps are needed.
First, the individual die I/O connections must be extended by adding copper pillars to them before over-molding. After the molding, the back of the molding must be grounded away to expose the pillars before attaching the RDL and forming the solder balls.
In the RDL-first approach, the RDL attaches to the carrier using a temporary release layer and the die attaches to the RDL. The assembly then gets over-molded, the carrier gets released, and the solder balls get formed. The final step for either approach is to separate the assemblies, which were formed en masse into individual devices.
These different approaches provide different cost and performance trade-offs. In terms of cost, the mold-first, face-down approach avoids the need for fabricating the copper pillars and for the back grinding, so it has a lower fabrication cost. It is best suited for low I/O count applications; however, there are issues with die shift, wafer warpage, and the like that limit its usage for complex multi-chip packaging.
The face-up approach reduces those issues and has an advantage in thermal management as the back of the chip is fully exposed, facilitating heat removal. The RTL-first approach has the advantage that it allows the use of known good die (KGD) in its fabrication, increasing yield.
In performance, the face-down approach has a shorter connection path than the other two approaches (Figure 2). Those two approaches have copper pillars that extend the connection to the RDL as well as having a layer of material under the chip that adds parasitic capacitance between the connections, affecting their high-frequency performance.
Figure 2 The choice of FOWLP approach can affect trace length and create parasitic effects that need accounting in the chip’s design. Source Micromachines
New tools for advanced packaging
Such subtle parasitic effects due to the package’s fabrication are increasingly important as logic speeds rise and can dramatically alter signal timing and characteristics. Thus, developers seeking to use such advanced packaging techniques will need to ensure that their simulations and design verification efforts include the package as well as the chip design to ensure success.
Chip vendors are starting to develop their own in-house tools that integrate the package and chip design into a single process flow for their customers. However, in-house tools may limit designer choices for the chips made with vendor processes. Those who want to mix chips from different processes may need to depend, instead, on tools that are available through outsourced assembly and test (OSAT) outfits to verify the full packaged chip design. The EDA companies are also stepping up to develop design and verification tools that can support these advanced packaging requirements.
Either way, the role of advanced packaging will continue to grow as the industry keeps pushing to keep Moore’s Law valid as long as possible. The demand for smaller, faster, more-capable chips and systems will continue, and packaging now looks to be the new frontier that developers will need to explore.
This article was originally published on EDN.
Rich Quinnell is a retired engineer and writer, and former Editor-in-Chief at EDN.