Here are some thoughts about a simple question: is analog EDA really an achievable thing? Blogger takes a closer look at different aspects.
To start, I am not a career analog design engineer. I have worked for years as an analog/RF design engineer, including a stint in analog/mixed-signal IC design and layout. I also studied control systems and machine learning (ML) pretty deeply for several years, and since then, I have kept marginally well up to date with the data science. These days, I do a good bit of consulting, RF contract design, and a lot of engineering writing. Hence, I am daily reading and researching various engineering, physics, and materials science topics that pertain to electronics, mostly RF and analog. What I am not doing daily is bludgeoning transistors into submission, running sims until my eyes bleed, or playing tetris in a layout editor to wrangle parasitics that are determined to make me look like a fool.
This is why I defer to our esteemed analog design engineer audience on the nuances and vagaries of analog. However, I do have thoughts every now and again. Today, I am having thoughts about a few different blogs and articles I have read about automating analog design. The blogs and articles I have read are mostly from electronic design automation (EDA) software companies. In these written works, I notice a general theme that whoever is writing them seems to believe that analog design, at least in a somewhat significant way, can be automated. I found these claims puzzling for a few different reasons.
Source: Siemens EDA
My training in analog design started with models of transistors and common circuit elements, ugly hand-drawn schematics with arrows in confusing directions, lots of math, and eventually days of confusion in front of circuit simulators. Later, after some more months, or years, spent in front of circuit simulators, I eventually graduated to layout and full circuit simulation, where I learned that everything I learned is a lie and the real world is cold dark place where your hopes of successful circuit design are more often than not dashed across a rocky shoreline like the broken timbers of unfortunate seacraft of the past.
After uncounted iterations of this process, I found that competency, and the firm hand of guidance from more seasoned engineers, eventually led to an almost reasonable grasp of how to approach an analog design problem from system level requirements to someone who is willing to roll the dice (pun intended) on in silicon. What I mostly learned though is that the folks that were considered “good” analog design engineers were also looked upon like dark wizards whose powers of sorcery were likely drawn from the realm of chaos itself.
I use the concept of chaos intentionally in that last analogy. My experience—and I could be wrong in regards to the latest in best practices—has been that analog design is as much experience as it is intuition and/or blind luck. Some of my evidence for this thought process has been my experience as a layout engineer tasked with somehow browbeating fields of polygons into obeying the whims of the design engineers whose clever circuits were far too picky about parasitics in their neighborhood. My solutions were born from a mix of a general understanding of physics as it pertains to semiconductors and what I thought might work if I could remember the right hotkey.
With that preamble out of the way, my question is simple: is analog design automation really an achievable thing? Tools like Monte Carlo analysis and setting up the right test bench are critical in design success, and that involves quite the learning curve. There is also a large amount of what I consider subjectivity involved in choosing circuit topologies. Adding to the mix the extremely complex models of advanced node processes and new transistor types (see FinFet), can any useful aspects of analog design be automated?
I want to make it clear that I am not talking about protecting jobs for analog design engineers who don’t want to be replaced by robot workers. Mine is a serious question. The articles I have read from prestigious and possibly monopolistic EDA software companies suggests that it is. However, when I dig deep into the articles, it seems to suggest that all that is really possible is aiding analog designers in iterating between the circuit schematic and layout portion faster
Again, in my limited experience, most analog designers didn’t do their own layout, and were only involved in layout when something goes horribly wrong. So, how does an ML algorithm that helps an analog designer with insights into the carnage parasitics will wreak on their designs in physical layout really help that much? My understanding is that you learn that after a few mistakes and trying not to die of shame during design meetings when the tape-out is delayed by months because of your arrogance.
Though compute power is much more readily available today than in the past, my thinking is that the computing resources to run an ML algorithm that babysits an analog designer during the mad scramble of the design process would have to be quite extensive. Simulating complex circuits is already resource intensive enough, and wouldn’t an ML algorithm essentially have to be running sims in the background while your work provides these insights?
In these articles, I see claims that computationally intelligent EDA tools can in effect go from a netlist to physical layout without human intervention. With the extreme quantity of variables in an analog design, many of which are strictly dependent on process and topology, can this actually work? I can see how with enough training, a given popular process focusing on common/often-used IP such an ML algorithm could effectively replicate a design process and perform the necessary tweaks to get an analog circuit working as long as efforts were taken to minimize the number of variables. At this point though, isn’t that just a parametric simulation?
From the little technical detail these articles have revealed, assumedly to protect some EDA IP, the ML algorithms that do this work on a functional model of the design space use a model based on functional behavior of the circuit to be designed. This sounds a good deal like basic control systems engineering. This model must be built by someone, such as an analog design engineer. Also, to train this ML algorithm, a dataset needs to be available.
Hence, similar designs from netlist to physical layout need to have been previously observed and recorded in such a way that they can be used to train an ML algorithm to reasonable accuracy. This process is also claimed to help with topology selection. Given the diversity of topologies and systems, I am curious how this would actually work. Wouldn’t an extensive topology library be needed? How is this topology library developed and described in such a way that an ML algorithm could suggest it to a designer?
My last thoughts have to do with where all of this training data comes from in the first place. Assuming that this ML algorithm must be trained on data from designs or systems that are somewhat similar, wouldn’t contributing to datasets for these algorithms be in some way sharing IP? What if the EDA tool’s ML systems are trained on designs from your competitor and the ML algorithm suggests topologies and solutions that closely resemble their IP? How is IP infringement avoided in these cases? Also, wouldn’t this only work on very common processes where there is a large enough set of designs and rich enough design data to build such a model?
And lastly, there are quite a few analog design houses that design analog circuits for a given process and sell the IP. Would tools like this effectively “steal” from these designers and make their special sauce available to others who use the ML algorithms developed from the sweat of contract designers?
As you can see, I am left with many questions about the validity and functional approach of automating analog design. I would like to know what the community thinks, and if contrary to my thinking, analog automation tools have progressed to a point that soon we will all just be serving our machine overlords.
This article was originally published on Planet Analog.
Jean-Jaques (JJ) DeLisle, an electrical engineering graduate (MS) from Rochester Institute of Technology, has a diverse background in analog and RF R&D, as well as technical writing/editing for engineering design publications. He writes about analog and RF for Planet Analog.