Power IC design for ESD and latchup tolerance requires an advanced approach based on iterative block-level verification.
Design of power/driver ICs in compliance with latchup qualification requirements involves a conceptually different approach in comparison with digital LV (low voltage) ICs. The LV ICs’ electrostatic discharge (ESD) and latchup design challenges are typically addressed at the level of I/O library cells that can be reused in a variety of products without customization.
The HV ICs usually combine several voltage domains isolated from the P-substrate. From a cost perspective, junction-isolated process technologies are dominant. They support so-called isolation N-pockets to enclose the devices and circuit blocks. In an extended CMOS (ECMOS) process, the pocket is formed by a set of deep N-well (DNW) implants. Due to the limits of deep implantation, this approach allows pocket voltage rating within a 40V range. A voltage range up to 120V can be achieved via a bipolar CMOS DMOS (BCD) process technology, where the N-pockets are formed by a combination of buried layers, optional sinkers, and a relatively thick grown N-epitaxial layer. The technologies integrate power-optimized complementary lateral DMOS devices with drain extension and either non-self-aligned or double diffusion scheme for source and body regions . The minimum process layout design rules for the pocket isolation are inadequate for latchup injection test. Instead, application-specific complex layout latchup design rules are necessary.
Overall, latchup design rules, standards, and checker descriptions infrequently explain the reasoning behind their methodological steps in conjunction with real design. Such an understanding often helps to organize the practical experience to be effective. The purpose of this article is to address the gap in understanding of such a diverse, novel, and complex subject as HV analog IC design from the latchup perspective. It is achieved below by connecting in a logical order the explanation of the latchup phenomenological physical effects presented on the semiconductor structure level followed by the introduction of injector-victim formalism for latchup collection features and prevention spacing rules. Then, a set of definitions is applied to the experimental methodology for latchup-spacing rule parameters and block-level verification principles toward the practical concept of the IC-latchup co-design. This article does not intend to provide a broad review of the HV latchup subject, either from an historical or diversity perspective. Instead, it is focused on a successfully verified-by-practice approach.
The latchup phenomenon is a side-effect of parasitic structures formed by the regions of integrated active devices. At the proximity of certain regions the injected carriers can diffuse and drift long distances in substrate, and at a certain current level initiate a non-linear conductivity modulation due to positive feedback between impact ionization, thermal carrier generation, and the parasitic bipolar gain. As a result, a temporary electrical regime deviation can induce a non-dedicated strong current path. It can further result in irreversible damage or formation of a conductive state that cannot self-dissipate as long as the original power supply regime remains unchanged – i.e., latchup. The latchup state is usually detected by comparison of the power-supply currents before and after the stimulus.
The latchup states can be induced either by current injection from forward-biased junction connected to I/O pins or by an overvoltage of power-supply pins during the test pulse. In a real environment the effect can be caused by power surges, electromagnetic interference (EMI) events, intermittent connection with inductive load, hot plug-in, and ionizing radiation. The latchup robustness is essentially an IC quality measure that represents an ability to withstand a certain level of the short-term electrical regime deviation and return to the original functional state without irreversible changes. Respectively, the qualification test according to the standard  emulates two events – the current injection in the I/O pins and the overvoltage of power-supply pins. Typical criterion is less than 10% change of all power-supply currents and passing of a full functional test program.
Thus, the latchup test essentially examines the stability of a particular IC design against relatively short-term deviations of the operation conditions of the pins interfacing with the environment. An analogy of a similar-purpose test for ESD conditions is the power-on mode system-level ESD test [3,4]. Due to the lack of coverage by conventional circuit simulation models, the latchup test pass level is hard to predict without a dedicated approach.
Phenomenological understanding of HV latchup
The specific of the HV IC latchup arises both for the overvoltage and injection latchup test modes. There are two main ratings related to elevated voltage levels – the maximum operating voltage (MOV) and absolute maximum voltage rating (AMR). Operation within MOV range guarantees long-term reliability, while increasing the voltage above AMR may cause an immediate irreversible failure. Respectively, for the range between MOV and AMR, a survivability is expected and, namely in this regime, the latchup test is accomplished. The uncertainty is related to correlation between the formal datasheet IC pin AMR voltage, which can be set as low as 10% over MOV, real physical AMR of the integrated devices connected to the pin, and real physical AMR of the IC pin with a particular layout design.
Propagated from LV digital ICs, the standard overvoltage test for the supply pin is defined up to the level of 1.5xMOV . The same level limits the voltage compliance for the injection current test if the current limit is not achieved. While this voltage level can be easily met in LV CMOS circuits, the HV circuits with power-optimized LDMOS will not always tolerate it. A way around this is the approach of maximum stress voltage (MSV), which limits the test voltage . The injection test induces the detection current between the HV pins, which may lead to high Joule heating.
However, the main specific of the HV latchup is related to the parasitic structures themselves. The easiest way to explain this is via a comparison with a more familiar LV latchup. The LV latchup typically involves the current path through the parasitic silicon-controlled rectifier (SCR) formed either inside the I/O cell or in the core circuit.
For example, in the push-pull I/O buffer (Fig. 1), the high-side (HS) hole injection from the PMOS body diode is stimulated when the output is pulled up above the power-supply level. At negative injection current test, the output is being pulled below the ground level (Fig.1) and the low-side (LS) electron injection is realized through the NMOS body diode. The high current path is formed between the p+-emitter and n+-emitter represented by the devices’ sources. In line with the physical effects, the latchup prevention rules require placement of the NMOS and PMOS devices with full isolation by the body tie rings to reduce the gain of n-p-n and p-n-p structures. Since the carriers are injected directly inside the SCR structure bases, the spacing rules have to control the guard rings’ length Lnbase and Lpbase (Fig.1). The reduced gain results in increased SCR holding voltage above the power-supply level, thus eliminating a physical possibility of the latchup state formation.
Figure 1 Equivalent structure cross-section to explain I/O latchup scenario with circuit diagrams for the latchup test for HS and LS injections with CMOS devices represented by their body diodes
Such IC I/O buffer latchup scenario and prevention rules, however, become absolutely irrelevant for HV technologies as long as the NMOS and PMOS devices are placed in separate N-pockets. Namely this approach presents a usual design practice that guarantees the passing level for LV I/O latchup at the minimum design rules for pocket isolation.
In the case of LV core latchup, the injecting junctions are located in the I/O cell area while the victim is represented by a core circuit. At high potential difference, the ESD diode carriers injected from the I/O may drift toward the core circuit, represented by the NMOS-PMOS inverter on the left of Fig. 2, and induce parasitic core SCR turn-on. The higher sensitivity of the core circuit is the result of the maximum body-to-source spacing rules utilization. Respectively, the prevention rules are intended to space apart the core circuit from the I/O injection source (length LII at Fig. 2).
Figure 2 Equivalent structure cross-section to explain core latchup scenario.
In line with the I/O circuits, the core latchup problem in HV process technologies is solved by isolation of the core circuit from the substrate in a separate N-pocket with a proper N-channel stop (NCS) ring at the periphery of the pocket. Thus, the main LV latchup practice is hardly useful for HV circuits that bring a different latchup specific of their own. The HV latchup is primarily caused by a different parasitic structure – pocket-to-pocket HV n-p-n turning on in injection conditions. For example, consider a pair of HV ESD diodes connected to an I/O pin (Fig. 3), with the N-epi pockets at different potential from the n-p-n structure with the high-side pocket acting as collector and the low-side pocket acting as emitter and the p-substrate ring as a base. The conditions of the injection realized at latchup test require both wider isolation spacing and additional collection rings.
Figure 3 Structure for HV latchup analysis and circuit diagrams for the HS hole and LS electron injection.
In the next level of details, the lateral pocket-to-substrate junction at high applied voltage acts somewhat differently in BCD and ECMOS technologies. With the pocket voltage increase in a BCD process, the space charge region is expanding inside the lightly doped Nepi region, creating a corresponding extracting electric field for the carriers injected inside the pocket. In the ECMOS process, the depletion region propagates mainly in the direction of the lightly doped P-substrate region. The absence of PBL in the ECMOS process reduces the efficiency of HS-injected holes collection by the P-sub ring.
In the LV circuit latchup, the parasitic SCR structure is capable to hold on-state regime due to a low holding voltage of ~1.5V in comparison with the power-supply level of 1.8-3.3V. Meantime, the parasitic n-p-n devices do not present a vulnerability due to relatively high “native” holding voltage of ~4-7V. In case of HV latchup, the holding voltage pocket-to-pocket n-p-n at minimum isolation spacing ranges from ~10-20V. Thus, for the HV latchup isolation, additional rules essentially have to target a shift of the critical regime for parasitic n-p-n structure conductivity modulation effects by reducing both the gain of the structure and the level of injection and also increasing the collection. In these conditions, the electro-thermal characteristics, the n-p-n, primarily determine the latchup robustness.
In the most common case, the LS injection latchup is initiated by the pocket pulled below the substrate potential. Less common is the case when the injection is from the forward-biased junction inside of the LS pocket (Fig. 4a). The injected electrons in the substrate (n-p-n base) region drift toward the HS pocket and change the electric field distribution, increasing the avalanche multiplication. To reduce the necessary pocket-to-pocket separation, two effective collecting features are used in addition to the p-substrate ring. At LS injection, to re-route at least part of the injected electrons away from the HS pocket, the N-moat ring can be connected to an LV power supply (Fig. 4a). Similarly, the HS hole injection conditions are suppressed by introducing a p-dummy collector inside the pocket of the HS injecting junction (Fig. 4b) to partially collect the holes inside the pocket.
Figure 4 Cross-section to explain the HV latchup scenarios with additional collection of the low-side electron injection with biased N-moat ring (a) and high-side holes with dummy p-collector (b).
Overall, the pocket-to-pocket spacing rules are a function of the applied voltage, injection current level, and the test temperature as well as the device design and size. Unlike LV latchup, the HV latchup is typically irreversible and results in IC burnout, unless accurate analysis of the detection current is made. The burnout of the pocket n-p-n structure is the result of either electrical or electro-thermal current instability followed by negative differential resistance, current filamentation formation, and local burnout.
HV latchup rules: Injector-victim formalism
Apparently not every pocket is forced to inject during IC latchup test. Nor can every N-pocket complement the current path acting as a “victim.” Therefore, the first step toward the co-design approach is detection of the pockets critical to latchup events. This requires definition and rules ideally compatible with future automated check recognition and verification procedures.
In spite of a number of alternative approaches, the most practical one is the so-called injector-victim formalism. Combining particular circuit datasheet pin specification with the latchup test standards, the latchup rule matrix can be set within only four kinds of pockets – HS and LS injectors and victims (Fig. 5).
The HS Injector can be defined as a pocket at HS potential if it contains a p-n junction that can be forced in forward current conduction (Fig. 5a). Any nearby LS potential pocket represents a complementary HS Victim pocket. In the injection conditions, a portion of the holes can escape from the HS injecting pocket and drift toward the HS victim pocket, causing latchup at some critical combination of the current density, voltage, temperature, and pocket spacing. For example, the relative separation between 80V biased injector and victim requires 15 times more distance in comparison with 10V bias.
Similarly, the LS Injector is defined as a pocket that either contains an inner junction or can be forward-biased during the latchup test conditions. The role of the LS Victim can be accomplished via a pocket electrically connected to an HS supply (Fig. 5b).
Figure 5 High-side hole injectors and victims (a). Low-side electron injectors and victims (b).
In spite of that the victims and injectors essentially form the collector or the emitter regions of HV parasitic n-p-n; the physical analogy remains quite apparent when visualizing burnout of the pocket-to-pocket spacing (Fig. 6).
Figure 6 Negative-mode current injection LU failure.
The optimal power IC design inevitably requires a thought-through placement of the HS and LS injectors and victims according to the additional spacing requirements. It involves grouping them together and using common collection rings. Such procedures are hardly effective if just based on an intuitive approach.
[Continue reading on EDN US: Wafer-level latch tests]
 V. A. Vashchenko and A. A. Shibkov. “ESD Design for Analog Circuits.” Springer 2010.
 IC Latch-Up Test JESD78E, JEDEC Solid State Technology Association, 2016.
 ISO 10605 Standard, 2008-07-15, ISO, Switzerland.
 ANSI/ESD SP 5.6-2009, “Electrostatic Discharge Sensitivity Testing – Human Metal Model (HMM),” 2009
 Calibre PERC LDL DRC Guide:, Mentor Graphic
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