Analog IPs for 4-nm and 3-nm process nodes in pipeline

Article By : Majeed Ahmad

Analog and mixed-signal IP suppliers are readying their offerings for process nodes spanning from 5nm to 3nm.

The transition to smaller process nodes has been seen as a major stumbling block for the analog design realm for quite some time, and that makes the recent announcement from Analog Bits regarding its IPs for TSMC’s 4 nm and 3 nm process geometries a notable premise. The supplier of low-power mixed-signal IPs made this announcement before presenting two technical papers on its IPs for 5-nm nodes at the 2021 TSMC Open Innovation Platform (OIP) Ecosystem Forum.

Analog Bits has also telegraphed its plans for IPs catering to TSMC’s 4 nm and 3 nm process nodes. The Sunnyvale, California-based IP firm is targeting its Analog Foundation IP at the high-end system-on-chips (SoCs) optimized for performance, power, or density. That’s a promising development which comes with strings attached and a clear message: when it comes to smaller nodes primarily designed for digital, analog engineers will have to do things differently.

For a start, while digital logic is getting cheaper in modern SoCs, not all analog functions can be incorporated economically. Then, there are certain analog building blocks that don’t scale adequately to smaller nodes. Last but not least, the transition from FinFET to gate-all-around (GAA) technology in advanced nodes will also bring unique engineering challenges like capacitance compensation.

However, as the Analog Bits announcement shows, the fundamental building blocks of high-performance analog are still available for smaller nodes. But analog integration at these advanced nodes will require much higher levels of mixed-signal circuit innovation. Moreover, analog and mixed-signal designs on 4 nm and 3 nm nodes will demand a new breed of toolchains to complement the traditional SPICE simulators.

Analog design is nothing without innovation and perseverance, whether it’s matching transistors or creating new power architectures. Now, analog designers, known for their ability to develop innovative circuits, are going to be tested once more. A new venue for a relentless design effort is awaiting them at 5 nm and smaller nodes.

This article was originally published on Planet Analog.

Majeed Ahmad, Editor-in-Chief of EDN, has covered the electronics design industry for more than two decades.


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