There has been vast progress in digital layout automation, which has made it possible to develop complex digital ICs quickly. However, analog layout techniques are still much the same as they were years ago...
There has been vast progress over the last 30 years or so in digital layout automation, which has made it possible to develop complex digital ICs relatively quickly. However, for analog layout, techniques are still much the same as they were years ago. True, there have been some improvements such as using parameterized cells to generate Design Rule Check (DRC) correct primitive devices, but placing them and carrying out power and signal routing is still largely a manual step. Electronic Design Automation (EDA) progress in the analog world seems to have stalled, despite the vastly increased computing power available today. There are reasons for this lack of progress.
The first is a general reluctance of analog layout engineers to approve layout generated by automated tools. When talking with layout people, even within the same company, different views are often expressed as to what is ‘correct’. Some form of editing the result is almost always needed, but the ability to edit the result should be done without going back to the pure polygon level editing that most layout editors force users to adopt. The automation needs to be there, but with the ability to control and/or correct the results.
Figure 1High level editing representation of the symmetric design. The red/green coloring represents symmetrical devices; grey coloring is for dummy devices. Guard rings are shown in blue.
The second reason for the lack of progress is more complex. Digital place & route (P&R) using standard cells eliminates the need for complex DRC checks of the base layers. For analog however, a much larger and more complex rule set must be followed if any attempt to automate the process is made. Unlike DRC in the digital layout world, when only rule violations need to be detected, during analog P&R, action needs to be taken to adhere to rules as the layout is formed and not having to rely on having some sort of post-layout fix up. Concurrent electrical awareness is required to ensure that some of the more complex requirements are met.
Figure 2The automatically generated placed layout. At the top are PMOS devices, below are NMOS devices in.
A modern automated approach to speed up layout therefore requires many considerations:
Modern automated tools, like Pulsic’s Animate, are now appearing in design flows and promise a significant acceleration of the layout cycle, without relinquishing the level of control analog designers require.